- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\01_gaoyun\gao_project\56_uart_ddr3_tft_hdmi_rgb2gray\uart_ddr3_tft_hdmi_rgb2gray\src\image_buffer\temp\FIFO\fifo_define.v H:\01_gaoyun\gao_project\56_uart_ddr3_tft_hdmi_rgb2gray\uart_ddr3_tft_hdmi_rgb2gray\src\image_buffer\temp\FIFO\fifo_parameter.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\edc.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-3
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Tue Aug 29 14:13:07 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | image_buffer
Synthesis Process | Running parser: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.449s, Peak memory usage = 39.570MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.570MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.570MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.570MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.570MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.570MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.570MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.570MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.570MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.570MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.570MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.570MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.314s, Peak memory usage = 44.469MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 44.469MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 44.469MB
Total Time and Memory Usage | CPU time = 0h 0m 0.794s, Elapsed time = 0h 0m 0.8s, Peak memory usage = 44.469MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 39
I/O Buf | 39
IBUF | 21
OBUF | 18
Register | 73
DFFPE | 5
DFFCE | 68
LUT | 95
LUT2 | 24
LUT3 | 31
LUT4 | 40
ALU | 10
ALU | 10
SSRAM | 3
RAM16S4 | 3
INV | 3
INV | 3
BSRAM | 1
SDPB | 1

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 126(98 LUT, 10 ALU, 3 RAM16) / 23040 | <1%
Register | 73 / 23685 | <1%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 73 / 23685 | <1%
BSRAM | 1 / 56 | 2%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | RdClk_ibuf/I
WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | WrClk_ibuf/I
fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n4_s2/O
fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n9_s2/O

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | RdClk | 100.0(MHz) | 123.8(MHz) | 6 | TOP
2 | WrClk | 100.0(MHz) | 299.4(MHz) | 5 | TOP
3 | fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
4 | fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | 1.923
Data Arrival Time | 8.878
Data Required Time | 10.801
From | fifo_inst/Equal.rq1_wptr_0_s8
To | fifo_inst/Empty_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 30 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 4 | fifo_inst/Equal.rq1_wptr_0_s8/CLK
6.239 | 5.376 | tC2Q | RR | 1 | fifo_inst/Equal.rq1_wptr_0_s8/DO[0]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.rq2_wptr_0_s4/I0
6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Equal.rq2_wptr_0_s4/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/n133_s0/I1
7.644 | 0.540 | tINS | RF | 1 | fifo_inst/n133_s0/COUT
7.644 | 0.000 | tNET | FF | 1 | fifo_inst/n134_s0/CIN
7.692 | 0.048 | tINS | FR | 1 | fifo_inst/n134_s0/COUT
7.692 | 0.000 | tNET | RR | 1 | fifo_inst/n135_s0/CIN
7.740 | 0.048 | tINS | RR | 1 | fifo_inst/n135_s0/COUT
7.740 | 0.000 | tNET | RR | 1 | fifo_inst/n136_s0/CIN
7.788 | 0.048 | tINS | RR | 1 | fifo_inst/n136_s0/COUT
7.788 | 0.000 | tNET | RR | 1 | fifo_inst/n137_s0/CIN
7.836 | 0.048 | tINS | RR | 1 | fifo_inst/n137_s0/COUT
7.836 | 0.000 | tNET | RR | 1 | fifo_inst/n138_s0/CIN
7.884 | 0.048 | tINS | RR | 1 | fifo_inst/n138_s0/COUT
7.884 | 0.000 | tNET | RR | 1 | fifo_inst/n139_s0/CIN
7.932 | 0.048 | tINS | RR | 1 | fifo_inst/n139_s0/COUT
7.932 | 0.000 | tNET | RR | 1 | fifo_inst/n140_s0/CIN
7.980 | 0.048 | tINS | RR | 1 | fifo_inst/n140_s0/COUT
7.980 | 0.000 | tNET | RR | 1 | fifo_inst/n141_s0/CIN
8.028 | 0.048 | tINS | RR | 1 | fifo_inst/n141_s0/COUT
8.028 | 0.000 | tNET | RR | 1 | fifo_inst/n142_s0/CIN
8.076 | 0.048 | tINS | RR | 1 | fifo_inst/n142_s0/COUT
8.256 | 0.180 | tNET | RR | 1 | fifo_inst/rempty_val_s1/I2
8.698 | 0.443 | tINS | RR | 1 | fifo_inst/rempty_val_s1/F
8.878 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 30 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Empty_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Empty_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 6
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.920, 23.952%; route: 0.720, 8.982%; tC2Q: 5.376, 67.066%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 2

Path Summary:

Slack | 6.660
Data Arrival Time | 4.141
Data Required Time | 10.801
From | fifo_inst/Full_s0
To | fifo_inst/Full_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | WrClk
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
0.683 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK
1.230 | 0.367 | tC2Q | RR | 7 | fifo_inst/Full_s0/Q
1.410 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_2_s1/I0
1.915 | 0.505 | tINS | RR | 21 | fifo_inst/Equal.wgraynext_2_s1/F
2.095 | 0.180 | tNET | RR | 1 | fifo_inst/wfull_val_s5/I1
2.591 | 0.496 | tINS | RR | 1 | fifo_inst/wfull_val_s5/F
2.771 | 0.180 | tNET | RR | 1 | fifo_inst/wfull_val_s1/I0
3.276 | 0.505 | tINS | RR | 1 | fifo_inst/wfull_val_s1/F
3.456 | 0.180 | tNET | RR | 1 | fifo_inst/wfull_val_s0/I0
3.961 | 0.505 | tINS | RR | 1 | fifo_inst/wfull_val_s0/F
4.141 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
10.682 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Full_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 3

Path Summary:

Slack | 6.660
Data Arrival Time | 4.141
Data Required Time | 10.801
From | fifo_inst/Full_s0
To | fifo_inst/Equal.wbin_8_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | WrClk
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
0.683 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK
1.230 | 0.367 | tC2Q | RR | 7 | fifo_inst/Full_s0/Q
1.410 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_2_s1/I0
1.915 | 0.505 | tINS | RR | 21 | fifo_inst/Equal.wgraynext_2_s1/F
2.095 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_6_s1/I0
2.600 | 0.505 | tINS | RR | 1 | fifo_inst/Equal.wgraynext_6_s1/F
2.780 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_8_s5/I0
3.285 | 0.505 | tINS | RR | 2 | fifo_inst/Equal.wbinnext_8_s5/F
3.465 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_8_s3/I1
3.961 | 0.496 | tINS | RR | 1 | fifo_inst/Equal.wbinnext_8_s3/F
4.141 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbin_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
10.682 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbin_8_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Equal.wbin_8_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 4

Path Summary:

Slack | 6.660
Data Arrival Time | 4.141
Data Required Time | 10.801
From | fifo_inst/Full_s0
To | fifo_inst/Equal.wbin_9_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | WrClk
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
0.683 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK
1.230 | 0.367 | tC2Q | RR | 7 | fifo_inst/Full_s0/Q
1.410 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_2_s1/I0
1.915 | 0.505 | tINS | RR | 21 | fifo_inst/Equal.wgraynext_2_s1/F
2.095 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_6_s1/I0
2.600 | 0.505 | tINS | RR | 1 | fifo_inst/Equal.wgraynext_6_s1/F
2.780 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_8_s5/I0
3.285 | 0.505 | tINS | RR | 2 | fifo_inst/Equal.wbinnext_8_s5/F
3.465 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_9_s3/I1
3.961 | 0.496 | tINS | RR | 1 | fifo_inst/Equal.wbinnext_9_s3/F
4.141 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbin_9_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
10.682 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbin_9_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Equal.wbin_9_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.011, 61.347%; route: 0.900, 27.452%; tC2Q: 0.367, 11.201%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 5

Path Summary:

Slack | 7.346
Data Arrival Time | 3.456
Data Required Time | 10.801
From | fifo_inst/Full_s0
To | fifo_inst/Equal.wbin_5_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | WrClk
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
0.683 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Full_s0/CLK
1.230 | 0.367 | tC2Q | RR | 7 | fifo_inst/Full_s0/Q
1.410 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_2_s1/I0
1.915 | 0.505 | tINS | RR | 21 | fifo_inst/Equal.wgraynext_2_s1/F
2.095 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wgraynext_5_s1/I1
2.591 | 0.496 | tINS | RR | 3 | fifo_inst/Equal.wgraynext_5_s1/F
2.771 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbinnext_5_s4/I0
3.276 | 0.505 | tINS | RR | 1 | fifo_inst/Equal.wbinnext_5_s4/F
3.456 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbin_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
10.682 | 0.683 | tINS | RR | 46 | WrClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Equal.wbin_5_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Equal.wbin_5_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 4
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.506, 58.075%; route: 0.720, 27.765%; tC2Q: 0.367, 14.160%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%