- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\01_gaoyun\gao_project\55_uart_ddr3_tft_hdmi\uart_ddr3_tft_hdmi\src\wr_data_fifo\temp\FIFO\fifo_define.v H:\01_gaoyun\gao_project\55_uart_ddr3_tft_hdmi\uart_ddr3_tft_hdmi\src\wr_data_fifo\temp\FIFO\fifo_parameter.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\edc.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-3
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Wed Aug 23 14:39:17 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | wr_data_fifo
Synthesis Process | Running parser: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.459s, Peak memory usage = 39.355MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.355MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.355MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.355MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.355MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.355MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.355MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.355MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.355MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.355MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.355MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.355MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.477s, Peak memory usage = 44.941MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 44.941MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 44.941MB
Total Time and Memory Usage | CPU time = 0h 0m 0.997s, Elapsed time = 0h 0m 1s, Peak memory usage = 44.941MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 176
I/O Buf | 176
IBUF | 21
OBUF | 155
Register | 95
DFFPE | 6
DFFCE | 89
LUT | 110
LUT2 | 20
LUT3 | 42
LUT4 | 48
ALU | 30
ALU | 30
SSRAM | 3
RAM16S4 | 3
INV | 4
INV | 4
BSRAM | 4
SDPB | 4

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 162(114 LUT, 30 ALU, 3 RAM16) / 23040 | <1%
Register | 95 / 23685 | <1%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 95 / 23685 | <1%
BSRAM | 4 / 56 | 8%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | RdClk_ibuf/I
WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | WrClk_ibuf/I
fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n4_s2/O
fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n9_s2/O

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | RdClk | 100.0(MHz) | 91.8(MHz) | 10 | TOP
2 | WrClk | 100.0(MHz) | 183.0(MHz) | 10 | TOP
3 | fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
4 | fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | -0.892
Data Arrival Time | 11.694
Data Required Time | 10.801
From | fifo_inst/Big.rq1_wptr_0_s12
To | fifo_inst/Almost_Empty_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Big.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 3 | fifo_inst/Big.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_7_s0/I0
6.924 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_7_s0/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_6_s1/I0
7.609 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_6_s1/F
7.789 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_5_s1/I0
8.294 | 0.505 | tINS | RR | 6 | fifo_inst/Big.wcount_r_5_s1/F
8.474 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_0_s0/I0
8.979 | 0.505 | tINS | RR | 1 | fifo_inst/Big.wcount_r_0_s0/F
9.159 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_0_s/I0
9.693 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_0_s/COUT
9.693 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_1_s/CIN
9.741 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_1_s/COUT
9.741 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_2_s/CIN
9.789 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_2_s/COUT
9.789 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/CIN
9.837 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.837 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.885 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.885 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.933 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.933 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.981 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.981 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
10.215 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_7_s/SUM
10.395 | 0.180 | tNET | RR | 1 | fifo_inst/arempty_val_s2/I2
10.838 | 0.443 | tINS | RR | 1 | fifo_inst/arempty_val_s2/F
11.018 | 0.180 | tNET | RR | 1 | fifo_inst/arempty_val_s0/I1
11.514 | 0.496 | tINS | RR | 1 | fifo_inst/arempty_val_s0/F
11.694 | 0.180 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Almost_Empty_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 10
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 4.015, 37.071%; route: 1.440, 13.295%; tC2Q: 5.376, 49.634%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 2

Path Summary:

Slack | 0.310
Data Arrival Time | 10.491
Data Required Time | 10.801
From | fifo_inst/Big.rq1_wptr_0_s12
To | fifo_inst/Rnum_9_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Big.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 3 | fifo_inst/Big.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_7_s0/I0
6.924 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_7_s0/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_6_s1/I0
7.609 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_6_s1/F
7.789 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_5_s1/I0
8.294 | 0.505 | tINS | RR | 6 | fifo_inst/Big.wcount_r_5_s1/F
8.474 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_0_s0/I0
8.979 | 0.505 | tINS | RR | 1 | fifo_inst/Big.wcount_r_0_s0/F
9.159 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_0_s/I0
9.693 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_0_s/COUT
9.693 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_1_s/CIN
9.741 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_1_s/COUT
9.741 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_2_s/CIN
9.789 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_2_s/COUT
9.789 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/CIN
9.837 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.837 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.885 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.885 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.933 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.933 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.981 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.981 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
10.029 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
10.029 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
10.077 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT
10.077 | 0.000 | tNET | RR | 1 | fifo_inst/rcnt_sub_9_s/CIN
10.311 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_9_s/SUM
10.491 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_9_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_9_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_9_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 8
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.173, 32.951%; route: 1.080, 11.216%; tC2Q: 5.376, 55.833%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 3

Path Summary:

Slack | 0.358
Data Arrival Time | 10.443
Data Required Time | 10.801
From | fifo_inst/Big.rq1_wptr_0_s12
To | fifo_inst/Rnum_8_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Big.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 3 | fifo_inst/Big.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_7_s0/I0
6.924 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_7_s0/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_6_s1/I0
7.609 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_6_s1/F
7.789 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_5_s1/I0
8.294 | 0.505 | tINS | RR | 6 | fifo_inst/Big.wcount_r_5_s1/F
8.474 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_0_s0/I0
8.979 | 0.505 | tINS | RR | 1 | fifo_inst/Big.wcount_r_0_s0/F
9.159 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_0_s/I0
9.693 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_0_s/COUT
9.693 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_1_s/CIN
9.741 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_1_s/COUT
9.741 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_2_s/CIN
9.789 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_2_s/COUT
9.789 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/CIN
9.837 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.837 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.885 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.885 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.933 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.933 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.981 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.981 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
10.029 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
10.029 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
10.263 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_8_s/SUM
10.443 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_8_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_8_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 8
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.125, 32.615%; route: 1.080, 11.273%; tC2Q: 5.376, 56.112%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 4

Path Summary:

Slack | 0.406
Data Arrival Time | 10.395
Data Required Time | 10.801
From | fifo_inst/Big.rq1_wptr_0_s12
To | fifo_inst/Rnum_7_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Big.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 3 | fifo_inst/Big.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_7_s0/I0
6.924 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_7_s0/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_6_s1/I0
7.609 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_6_s1/F
7.789 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_5_s1/I0
8.294 | 0.505 | tINS | RR | 6 | fifo_inst/Big.wcount_r_5_s1/F
8.474 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_0_s0/I0
8.979 | 0.505 | tINS | RR | 1 | fifo_inst/Big.wcount_r_0_s0/F
9.159 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_0_s/I0
9.693 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_0_s/COUT
9.693 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_1_s/CIN
9.741 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_1_s/COUT
9.741 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_2_s/CIN
9.789 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_2_s/COUT
9.789 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/CIN
9.837 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.837 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.885 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.885 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.933 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.933 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.981 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.981 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
10.215 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_7_s/SUM
10.395 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_7_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_7_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 8
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.077, 32.276%; route: 1.080, 11.329%; tC2Q: 5.376, 56.395%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 5

Path Summary:

Slack | 0.454
Data Arrival Time | 10.347
Data Required Time | 10.801
From | fifo_inst/Big.rq1_wptr_0_s12
To | fifo_inst/Rnum_6_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Big.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 3 | fifo_inst/Big.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_7_s0/I0
6.924 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_7_s0/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_6_s1/I0
7.609 | 0.505 | tINS | RR | 2 | fifo_inst/Big.wcount_r_6_s1/F
7.789 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_5_s1/I0
8.294 | 0.505 | tINS | RR | 6 | fifo_inst/Big.wcount_r_5_s1/F
8.474 | 0.180 | tNET | RR | 1 | fifo_inst/Big.wcount_r_0_s0/I0
8.979 | 0.505 | tINS | RR | 1 | fifo_inst/Big.wcount_r_0_s0/F
9.159 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_0_s/I0
9.693 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_0_s/COUT
9.693 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_1_s/CIN
9.741 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_1_s/COUT
9.741 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_2_s/CIN
9.789 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_2_s/COUT
9.789 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/CIN
9.837 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.837 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.885 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.885 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.933 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.933 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
10.167 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_6_s/SUM
10.347 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 42 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_6_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_6_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 7
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.029, 31.933%; route: 1.080, 11.387%; tC2Q: 5.376, 56.680%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%