- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\01_gaoyun\gao_project\55_uart_ddr3_tft_hdmi\uart_ddr3_tft_hdmi\src\rd_data_fifo\temp\FIFO\fifo_define.v H:\01_gaoyun\gao_project\55_uart_ddr3_tft_hdmi\uart_ddr3_tft_hdmi\src\rd_data_fifo\temp\FIFO\fifo_parameter.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\edc.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-3
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Wed Aug 23 14:38:29 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | rd_data_fifo
Synthesis Process | Running parser: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.537s, Peak memory usage = 39.590MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.590MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.590MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.590MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 39.590MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.590MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.590MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.590MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.590MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 39.590MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.590MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.590MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.078MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 46.078MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 46.078MB
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.078MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 176
I/O Buf | 176
IBUF | 133
OBUF | 43
Register | 95
DFFPE | 6
DFFCE | 89
LUT | 345
LUT2 | 36
LUT3 | 86
LUT4 | 223
ALU | 32
ALU | 32
SSRAM | 3
RAM16S4 | 3
INV | 5
INV | 5
BSRAM | 4
SDPB | 4

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 400(350 LUT, 32 ALU, 3 RAM16) / 23040 | 2%
Register | 95 / 23685 | <1%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 95 / 23685 | <1%
BSRAM | 4 / 56 | 8%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | RdClk_ibuf/I
WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | WrClk_ibuf/I
fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n4_s2/O
fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n9_s2/O

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | RdClk | 100.0(MHz) | 91.2(MHz) | 11 | TOP
2 | WrClk | 100.0(MHz) | 165.4(MHz) | 11 | TOP
3 | fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
4 | fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | -0.961
Data Arrival Time | 11.762
Data Required Time | 10.801
From | fifo_inst/Small.rq1_wptr_0_s12
To | fifo_inst/Almost_Empty_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/I0
6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
7.547 | 0.443 | tINS | RR | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
7.727 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
7.978 | 0.252 | tINS | RR | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
8.158 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
8.664 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
8.844 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/I0
9.378 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.378 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.426 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.426 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.474 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.474 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.522 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.522 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
9.570 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
9.570 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
9.618 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT
9.618 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_9_s/CIN
9.852 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_9_s/SUM
10.032 | 0.180 | tNET | RR | 1 | fifo_inst/arempty_val_s3/I1
10.527 | 0.496 | tINS | RR | 1 | fifo_inst/arempty_val_s3/F
10.707 | 0.180 | tNET | RR | 1 | fifo_inst/arempty_val_s2/I2
11.150 | 0.443 | tINS | RR | 1 | fifo_inst/arempty_val_s2/F
11.330 | 0.180 | tNET | RR | 1 | fifo_inst/arempty_val_s0/I3
11.582 | 0.252 | tINS | RR | 1 | fifo_inst/arempty_val_s0/F
11.762 | 0.180 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Almost_Empty_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 11
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.904, 35.814%; route: 1.620, 14.863%; tC2Q: 5.376, 49.323%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 2

Path Summary:

Slack | 0.626
Data Arrival Time | 10.176
Data Required Time | 10.801
From | fifo_inst/Small.rq1_wptr_0_s12
To | fifo_inst/Rnum_12_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/I0
6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
7.547 | 0.443 | tINS | RR | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
7.727 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
7.978 | 0.252 | tINS | RR | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
8.158 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
8.664 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
8.844 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/I0
9.378 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.378 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.426 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.426 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.474 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.474 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.522 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.522 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
9.570 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
9.570 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
9.618 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT
9.618 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_9_s/CIN
9.666 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_9_s/COUT
9.666 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_10_s/CIN
9.714 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_10_s/COUT
9.714 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_11_s/CIN
9.762 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_11_s/COUT
9.762 | 0.000 | tNET | RR | 1 | fifo_inst/rcnt_sub_12_s/CIN
9.996 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_12_s/SUM
10.176 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_12_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_12_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_12_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 8
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.857, 30.679%; route: 1.080, 11.596%; tC2Q: 5.376, 57.725%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 3

Path Summary:

Slack | 0.674
Data Arrival Time | 10.128
Data Required Time | 10.801
From | fifo_inst/Small.rq1_wptr_0_s12
To | fifo_inst/Rnum_11_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/I0
6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
7.547 | 0.443 | tINS | RR | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
7.727 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
7.978 | 0.252 | tINS | RR | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
8.158 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
8.664 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
8.844 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/I0
9.378 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.378 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.426 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.426 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.474 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.474 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.522 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.522 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
9.570 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
9.570 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
9.618 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT
9.618 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_9_s/CIN
9.666 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_9_s/COUT
9.666 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_10_s/CIN
9.714 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_10_s/COUT
9.714 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_11_s/CIN
9.948 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_11_s/SUM
10.128 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_11_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_11_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_11_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 8
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.809, 30.320%; route: 1.080, 11.657%; tC2Q: 5.376, 58.023%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 4

Path Summary:

Slack | 0.722
Data Arrival Time | 10.080
Data Required Time | 10.801
From | fifo_inst/Small.rq1_wptr_0_s12
To | fifo_inst/Rnum_10_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/I0
6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
7.547 | 0.443 | tINS | RR | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
7.727 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
7.978 | 0.252 | tINS | RR | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
8.158 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
8.664 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
8.844 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/I0
9.378 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.378 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.426 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.426 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.474 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.474 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.522 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.522 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
9.570 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
9.570 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
9.618 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT
9.618 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_9_s/CIN
9.666 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_9_s/COUT
9.666 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_10_s/CIN
9.900 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_10_s/SUM
10.080 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_10_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_10_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_10_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 8
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.761, 29.957%; route: 1.080, 11.717%; tC2Q: 5.376, 58.326%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 5

Path Summary:

Slack | 0.770
Data Arrival Time | 10.032
Data Required Time | 10.801
From | fifo_inst/Small.rq1_wptr_0_s12
To | fifo_inst/Rnum_9_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 2 | fifo_inst/Small.rq1_wptr_0_s12/CLK
6.239 | 5.376 | tC2Q | RR | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[1]
6.419 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/I0
6.924 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
7.104 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
7.547 | 0.443 | tINS | RR | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
7.727 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
7.978 | 0.252 | tINS | RR | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
8.158 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
8.664 | 0.505 | tINS | RR | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
8.844 | 0.180 | tNET | RR | 2 | fifo_inst/rcnt_sub_3_s/I0
9.378 | 0.534 | tINS | RF | 1 | fifo_inst/rcnt_sub_3_s/COUT
9.378 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_4_s/CIN
9.426 | 0.048 | tINS | FR | 1 | fifo_inst/rcnt_sub_4_s/COUT
9.426 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_5_s/CIN
9.474 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_5_s/COUT
9.474 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_6_s/CIN
9.522 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_6_s/COUT
9.522 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_7_s/CIN
9.570 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_7_s/COUT
9.570 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_8_s/CIN
9.618 | 0.048 | tINS | RR | 1 | fifo_inst/rcnt_sub_8_s/COUT
9.618 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_9_s/CIN
9.852 | 0.234 | tINS | RR | 2 | fifo_inst/rcnt_sub_9_s/SUM
10.032 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_9_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_9_s0/CLK
10.801 | -0.061 | tSu |  | 1 | fifo_inst/Rnum_9_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 7
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 2.713, 29.590%; route: 1.080, 11.779%; tC2Q: 5.376, 58.631%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%