- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v H:\0_gaoyun_p\1.9.9Beta-3\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-3
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Tue Aug 29 15:07:20 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | shift_reg_ram
Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.211s, Peak memory usage = 33.816MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.816MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.816MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.816MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.816MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 33.816MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.816MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 33.816MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 33.816MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.194s, Peak memory usage = 35.766MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 35.766MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 35.766MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 1s, Peak memory usage = 53.957MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.229s, Peak memory usage = 53.957MB Generate output files: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.389s, Peak memory usage = 66.410MB
Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 66.410MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 18
I/O Buf | 18
IBUF | 10
OBUF | 8
Register | 4113
DFFRE | 4096
DFFCE | 17
LUT | 2726
LUT2 | 11
LUT3 | 2131
LUT4 | 584

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 2726(2726 LUT, 0 ALU) / 23040 | 12%
Register | 4113 / 23685 | 18%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 4113 / 23685 | 18%
BSRAM | 0 / 56 | 0%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | clk_ibuf/I

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | clk | 100.0(MHz) | 255.5(MHz) | 4 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | 6.086
Data Arrival Time | 4.716
Data Required Time | 10.801
From | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[0]_s0
To | u_RAM_based_shift_reg/wdata_q_0_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[0]_s0/CLK
1.230 | 0.367 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[0]_s0/Q
1.410 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1252/I0
1.915 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1252/F
2.095 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1121/I0
2.226 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1121/O
2.406 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1055/I1
2.489 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1055/O
2.669 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1022/I1
2.751 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s1022/O
2.931 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s992/I0
3.014 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_255_G[8]_s992/O
3.194 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s7/I0
3.699 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s7/F
3.879 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s3/I0
4.010 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s3/O
4.190 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s1/I0
4.273 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s1/O
4.453 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s0/I0
4.536 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s0/O
4.716 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_0_s0/CLK
10.801 | -0.061 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_0_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 4
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.686, 43.756%; route: 1.800, 46.714%; tC2Q: 0.367, 9.530%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 2

Path Summary:

Slack | 6.086
Data Arrival Time | 4.716
Data Required Time | 10.801
From | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[1]_s0
To | u_RAM_based_shift_reg/wdata_q_1_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[1]_s0/CLK
1.230 | 0.367 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[1]_s0/Q
1.410 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1252/I0
1.915 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1252/F
2.095 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1121/I0
2.226 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1121/O
2.406 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1055/I1
2.489 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1055/O
2.669 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1022/I1
2.751 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s1022/O
2.931 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s992/I0
3.014 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_766_G[8]_s992/O
3.194 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s7/I0
3.699 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s7/F
3.879 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s3/I0
4.010 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s3/O
4.190 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s1/I0
4.273 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s1/O
4.453 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s0/I0
4.536 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[0]_s0/O
4.716 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_1_s0/CLK
10.801 | -0.061 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_1_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 4
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.686, 43.756%; route: 1.800, 46.714%; tC2Q: 0.367, 9.530%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 3

Path Summary:

Slack | 6.086
Data Arrival Time | 4.716
Data Required Time | 10.801
From | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[2]_s0
To | u_RAM_based_shift_reg/wdata_q_2_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[2]_s0/CLK
1.230 | 0.367 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[2]_s0/Q
1.410 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1252/I0
1.915 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1252/F
2.095 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1121/I0
2.226 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1121/O
2.406 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1055/I1
2.489 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1055/O
2.669 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1022/I1
2.751 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s1022/O
2.931 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s992/I0
3.014 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1277_G[8]_s992/O
3.194 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s7/I0
3.699 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s7/F
3.879 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s3/I0
4.010 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s3/O
4.190 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s1/I0
4.273 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s1/O
4.453 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s0/I0
4.536 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1022_G[0]_s0/O
4.716 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_2_s0/CLK
10.801 | -0.061 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_2_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 4
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.686, 43.756%; route: 1.800, 46.714%; tC2Q: 0.367, 9.530%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 4

Path Summary:

Slack | 6.086
Data Arrival Time | 4.716
Data Required Time | 10.801
From | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[3]_s0
To | u_RAM_based_shift_reg/wdata_q_3_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[3]_s0/CLK
1.230 | 0.367 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[3]_s0/Q
1.410 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1252/I0
1.915 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1252/F
2.095 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1121/I0
2.226 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1121/O
2.406 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1055/I1
2.489 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1055/O
2.669 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1022/I1
2.751 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s1022/O
2.931 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s992/I0
3.014 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1788_G[8]_s992/O
3.194 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s7/I0
3.699 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s7/F
3.879 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s3/I0
4.010 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s3/O
4.190 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s1/I0
4.273 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s1/O
4.453 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s0/I0
4.536 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1533_G[0]_s0/O
4.716 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_3_s0/CLK
10.801 | -0.061 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_3_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 4
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.686, 43.756%; route: 1.800, 46.714%; tC2Q: 0.367, 9.530%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 5

Path Summary:

Slack | 6.086
Data Arrival Time | 4.716
Data Required Time | 10.801
From | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[4]_s0
To | u_RAM_based_shift_reg/wdata_q_4_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[4]_s0/CLK
1.230 | 0.367 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_96_G[4]_s0/Q
1.410 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1252/I0
1.915 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1252/F
2.095 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1121/I0
2.226 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1121/O
2.406 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1055/I1
2.489 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1055/O
2.669 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1022/I1
2.751 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s1022/O
2.931 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s992/I0
3.014 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2299_G[8]_s992/O
3.194 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s7/I0
3.699 | 0.505 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s7/F
3.879 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s3/I0
4.010 | 0.131 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s3/O
4.190 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s1/I0
4.273 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s1/O
4.453 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s0/I0
4.536 | 0.083 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2044_G[0]_s0/O
4.716 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 4113 | clk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_4_s0/CLK
10.801 | -0.061 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_4_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 4
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 1.686, 43.756%; route: 1.800, 46.714%; tC2Q: 0.367, 9.530%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%