- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\0_gaoyun_p\1.9.9Beta_5\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg_top.v H:\0_gaoyun_p\1.9.9Beta_5\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\RAMBasedShiftRegister\data\RAM_based_shift_reg.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-5
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Fri Oct 13 09:58:09 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | c_shift_ram_0
Synthesis Process | Running parser: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.211s, Peak memory usage = 33.938MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.938MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.938MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.938MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 33.938MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.194s, Peak memory usage = 44.172MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 44.250MB Inferring Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 44.855MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 44.902MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.434s, Peak memory usage = 49.051MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 49.051MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 49.051MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 65.469MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.494s, Peak memory usage = 65.469MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 108.281MB
Total Time and Memory Usage | CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 108.281MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 19
I/O Buf | 19
IBUF | 11
OBUF | 8
Register | 8211
DFFRE | 8192
DFFCE | 19
LUT | 5425
LUT2 | 31
LUT3 | 4231
LUT4 | 1163

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 5425(5425 LUT, 0 ALU) / 23040 | 24%
Register | 8211 / 23685 | 35%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 8211 / 23685 | 35%
BSRAM | 0 / 56 | 0%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | clk_ibuf/I

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | clk | 100.0(MHz) | 229.8(MHz) | 5 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | 5.649
Data Arrival Time | 5.157
Data Required Time | 10.806
From | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[0]_s0
To | u_RAM_based_shift_reg/wdata_q_0_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
0.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[0]_s0/CLK
1.253 | 0.382 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[0]_s0/Q
1.440 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2720/I0
1.966 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2720/F
2.154 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2351/I0
2.290 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2351/O
2.477 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2166/I1
2.564 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2166/O
2.751 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2074/I0
2.838 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s2074/O
3.025 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s1998/I0
3.111 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_511_G[9]_s1998/O
3.299 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s22/I0
3.825 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s22/F
4.013 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s10/I1
4.149 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s10/O
4.336 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s4/I1
4.423 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s4/O
4.610 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s1/I1
4.696 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s1/O
4.884 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s0/I0
4.970 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_0_G[0]_s0/O
5.157 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
10.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_0_s0/CLK
10.806 | -0.064 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_0_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: | cell: 1.842, 42.974%; route: 2.063, 48.105%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%

### Path 2

Path Summary:

Slack | 5.649
Data Arrival Time | 5.157
Data Required Time | 10.806
From | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[1]_s0
To | u_RAM_based_shift_reg/wdata_q_1_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
0.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[1]_s0/CLK
1.253 | 0.382 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[1]_s0/Q
1.440 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2720/I0
1.966 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2720/F
2.154 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2351/I0
2.290 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2351/O
2.477 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2166/I1
2.564 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2166/O
2.751 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2074/I0
2.838 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s2074/O
3.025 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s1998/I0
3.111 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1534_G[9]_s1998/O
3.299 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s22/I0
3.825 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s22/F
4.013 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s10/I1
4.149 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s10/O
4.336 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s4/I1
4.423 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s4/O
4.610 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s1/I1
4.696 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s1/O
4.884 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s0/I0
4.970 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_1023_G[0]_s0/O
5.157 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
10.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_1_s0/CLK
10.806 | -0.064 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_1_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: | cell: 1.842, 42.974%; route: 2.063, 48.105%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%

### Path 3

Path Summary:

Slack | 5.649
Data Arrival Time | 5.157
Data Required Time | 10.806
From | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[2]_s0
To | u_RAM_based_shift_reg/wdata_q_2_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
0.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[2]_s0/CLK
1.253 | 0.382 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[2]_s0/Q
1.440 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2720/I0
1.966 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2720/F
2.154 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2351/I0
2.290 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2351/O
2.477 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2166/I1
2.564 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2166/O
2.751 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2074/I0
2.838 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s2074/O
3.025 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s1998/I0
3.111 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2557_G[9]_s1998/O
3.299 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s22/I0
3.825 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s22/F
4.013 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s10/I1
4.149 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s10/O
4.336 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s4/I1
4.423 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s4/O
4.610 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s1/I1
4.696 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s1/O
4.884 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s0/I0
4.970 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_2046_G[0]_s0/O
5.157 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
10.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_2_s0/CLK
10.806 | -0.064 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_2_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: | cell: 1.842, 42.974%; route: 2.063, 48.105%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%

### Path 4

Path Summary:

Slack | 5.649
Data Arrival Time | 5.157
Data Required Time | 10.806
From | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[3]_s0
To | u_RAM_based_shift_reg/wdata_q_3_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
0.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[3]_s0/CLK
1.253 | 0.382 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[3]_s0/Q
1.440 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2720/I0
1.966 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2720/F
2.154 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2351/I0
2.290 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2351/O
2.477 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2166/I1
2.564 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2166/O
2.751 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2074/I0
2.838 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s2074/O
3.025 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s1998/I0
3.111 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3580_G[9]_s1998/O
3.299 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s22/I0
3.825 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s22/F
4.013 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s10/I1
4.149 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s10/O
4.336 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s4/I1
4.423 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s4/O
4.610 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s1/I1
4.696 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s1/O
4.884 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s0/I0
4.970 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_3069_G[0]_s0/O
5.157 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
10.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_3_s0/CLK
10.806 | -0.064 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_3_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: | cell: 1.842, 42.974%; route: 2.063, 48.105%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%

### Path 5

Path Summary:

Slack | 5.649
Data Arrival Time | 5.157
Data Required Time | 10.806
From | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[4]_s0
To | u_RAM_based_shift_reg/wdata_q_4_s0
Launch Clk | clk[R]
Latch Clk | clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | clk
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
0.683 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
0.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[4]_s0/CLK
1.253 | 0.382 | tC2Q | RR | 1 | u_RAM_based_shift_reg/mem_mem_RAMREG_142_G[4]_s0/Q
1.440 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2720/I0
1.966 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2720/F
2.154 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2351/I0
2.290 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2351/O
2.477 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2166/I1
2.564 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2166/O
2.751 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2074/I0
2.838 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s2074/O
3.025 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s1998/I0
3.111 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4603_G[9]_s1998/O
3.299 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s22/I0
3.825 | 0.526 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s22/F
4.013 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s10/I1
4.149 | 0.136 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s10/O
4.336 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s4/I1
4.423 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s4/O
4.610 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s1/I1
4.696 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s1/O
4.884 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s0/I0
4.970 | 0.086 | tINS | RR | 1 | u_RAM_based_shift_reg/mem_RAMOUT_4092_G[0]_s0/O
5.157 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | clk
10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I
10.682 | 0.683 | tINS | RR | 8211 | clk_ibuf/O
10.870 | 0.188 | tNET | RR | 1 | u_RAM_based_shift_reg/wdata_q_4_s0/CLK
10.806 | -0.064 | tSu |  | 1 | u_RAM_based_shift_reg/wdata_q_4_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 5
Arrival Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%
Arrival Data Path Delay: | cell: 1.842, 42.974%; route: 2.063, 48.105%; tC2Q: 0.382, 8.921%
Required Clock Path Delay: | cell: 0.683, 78.448%; route: 0.188, 21.552%