- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\DVP_Capture\DVP_Capture.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\RAW2RGB.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\c_shift_ram_0\c_shift_ram_0.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\camera_init\camera_init.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\camera_init\i2c_control\i2c_bit_shift.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\camera_init\i2c_control\i2c_control.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\camera_init\ov5640_init_table_jpeg.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\camera_init\ov5640_init_table_rgb.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\camera_pll\camera_pll.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\ddr3_memory_interface\ddr3_memory_interface.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\ddr_pll\ddr_pll.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\gowin_ddr\gowin_ddr.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\gowin_pll\gowin_pll.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\ov5640_ddr3_raw2rgb_tft.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\rd_data_fifo\rd_data_fifo.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\vga\disp_driver.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\vga\disp_parameter_cfg.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\vga\dvi_encoder.v H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\wr_data_fifo\wr_data_fifo.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-5
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Fri Oct 13 10:01:57 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | ov5640_ddr3_raw2rgb_tft
Synthesis Process | Running parser: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 522.750MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.459s, Peak memory usage = 522.750MB Optimizing Phase 1: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.379s, Peak memory usage = 522.750MB Optimizing Phase 2: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.722s, Peak memory usage = 522.750MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 522.750MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 522.750MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.089s, Peak memory usage = 522.750MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 522.750MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.827s, Peak memory usage = 522.750MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.246s, Peak memory usage = 522.750MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 522.750MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 522.750MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.495s, Peak memory usage = 522.750MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 522.750MB
Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 522.750MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 91
I/O Buf | 88
IBUF | 13
OBUF | 53
TBUF | 2
IOBUF | 17
ELVDS_OBUF | 1
ELVDS_IOBUF | 2
Register | 11728
DFFSE | 1
DFFRE | 8913
DFFPE | 77
DFFCE | 2737
LUT | 8865
LUT2 | 558
LUT3 | 5712
LUT4 | 2595
ALU | 229
ALU | 229
SSRAM | 6
RAM16S4 | 6
INV | 39
INV | 39
IOLOGIC | 76
IDES8_MEM | 16
OSER8 | 24
OSER8_MEM | 20
IODELAY | 16
BSRAM | 21
SDPB | 12
SDPX9B | 8
pROM | 1
CLOCK | 7
CLKDIV | 1
DQS | 2
DCE | 1
DDRDLL | 1
DHCE | 1
PLLA | 1

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 9169(8904 LUT, 229 ALU, 6 RAM16) / 23040 | 40%
Register | 11728 / 23685 | 50%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 11728 / 23685 | 50%
BSRAM | 21 / 56 | 38%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk50m | Base | 20.000 | 50.0 | 0.000 | 10.000 |  |  | clk50m_ibuf/I
camera_pclk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | camera_pclk_ibuf/I
ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_s2/O
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_s2/O
RAW2RGB/clk_ce | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | RAW2RGB/DCE/CLKOUT
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 41.250 | 24.2 | 0.000 | 20.625 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT1
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 5.000 | 200.0 | 0.000 | 2.500 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT2
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 30.000 | 33.3 | 0.000 | 15.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT3
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | Gowin_PLL/PLLA_inst/CLKOUT2 | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | camera_pclk | 100.0(MHz) | 205.5(MHz) | 7 | TOP
2 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP
3 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP
4 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP
5 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1577.9(MHz) | 1 | TOP
6 | RAW2RGB/clk_ce | 100.0(MHz) | 229.8(MHz) | 5 | TOP
7 | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | 50.0(MHz) | 228.1(MHz) | 6 | TOP
8 | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | 200.0(MHz) | 1489.2(MHz) | 1 | TOP
9 | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | 33.3(MHz) | 168.8(MHz) | 10 | TOP
10 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 142.4(MHz) | 9 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | 0.863
Data Arrival Time | 19.384
Data Required Time | 20.248
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
15.000 | 0.000 |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT2
16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2
19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F
19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.159 | 0.159 | tCL | RR | 3254 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK
20.311 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
20.248 | -0.064 | tSu |  | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0

Path Statistics:

Clock Skew: | -0.855
Setup Relationship: | 5.000
Logic Level: | 6
Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%
Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890%
Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%

### Path 2

Path Summary:

Slack | 0.863
Data Arrival Time | 19.384
Data Required Time | 20.248
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
15.000 | 0.000 |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT2
16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2
19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F
19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.159 | 0.159 | tCL | RR | 3254 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK
20.311 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
20.248 | -0.064 | tSu |  | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0

Path Statistics:

Clock Skew: | -0.855
Setup Relationship: | 5.000
Logic Level: | 6
Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%
Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890%
Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%

### Path 3

Path Summary:

Slack | 0.863
Data Arrival Time | 19.384
Data Required Time | 20.248
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
15.000 | 0.000 |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT2
16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I2
19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F
19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.159 | 0.159 | tCL | RR | 3254 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK
20.311 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
20.248 | -0.064 | tSu |  | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0

Path Statistics:

Clock Skew: | -0.855
Setup Relationship: | 5.000
Logic Level: | 6
Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%
Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890%
Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%

### Path 4

Path Summary:

Slack | 0.863
Data Arrival Time | 19.384
Data Required Time | 20.248
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
15.000 | 0.000 |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT2
16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/I2
19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/F
19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.159 | 0.159 | tCL | RR | 3254 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK
20.311 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
20.248 | -0.064 | tSu |  | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0

Path Statistics:

Clock Skew: | -0.855
Setup Relationship: | 5.000
Logic Level: | 6
Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%
Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890%
Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%

### Path 5

Path Summary:

Slack | 0.863
Data Arrival Time | 19.384
Data Required Time | 20.248
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
15.000 | 0.000 |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
15.832 | 0.831 | tCL | RR | 1 | Gowin_PLL/PLLA_inst/CLKOUT2
16.019 | 0.188 | tNET | RR | 3 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
16.201 | 0.182 | tINS | RR | 64 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.389 | 0.188 | tNET | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.795 | 0.406 | tINS | RR | 8 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_dll/STEP[0]
16.982 | 0.188 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/I1
17.545 | 0.563 | tINS | RF | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s16/COUT
17.545 | 0.000 | tNET | FF | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/CIN
17.594 | 0.050 | tINS | FR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s17/COUT
17.594 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/CIN
17.645 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
17.645 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
17.694 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
17.694 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
17.744 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
17.744 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
17.795 | 0.050 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
17.795 | 0.000 | tNET | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
17.844 | 0.050 | tINS | RR | 2 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
18.032 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
18.548 | 0.516 | tINS | RR | 9 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
18.736 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/I2
19.197 | 0.461 | tINS | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/F
19.384 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
20.000 | 0.000 |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.159 | 0.159 | tCL | RR | 3254 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.346 | 0.188 | tNET | RR | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK
20.311 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
20.248 | -0.064 | tSu |  | 1 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0

Path Statistics:

Clock Skew: | -0.855
Setup Relationship: | 5.000
Logic Level: | 6
Arrival Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%
Arrival Data Path Delay: | cell: 2.246, 70.551%; route: 0.750, 23.559%; tC2Q: 0.188, 5.890%
Required Clock Path Delay: | cell: 0.182, 49.256%; route: 0.188, 50.744%