- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\01_gaoyun\gao_project\53_ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\src\rd_data_fifo\temp\FIFO\fifo_define.v H:\01_gaoyun\gao_project\53_ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\ov5640_ddr3_hdmi\src\rd_data_fifo\temp\FIFO\fifo_parameter.v H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\edc.v H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\fifo.v H:\0_gaoyun_p\1.9.9Beta-2\Gowin\Gowin_V1.9.9Beta-2\IDE\ipcore\FIFO\data\fifo_top.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-2
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Created Time | Fri Aug 18 10:02:17 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | rd_data_fifo
Synthesis Process | Running parser: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.524s, Peak memory usage = 39.188MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.188MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.188MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.188MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 39.188MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.188MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 39.188MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.188MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.188MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 39.188MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.188MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.188MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.227MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 46.227MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 46.227MB
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 46.227MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 176
I/O Buf | 176
IBUF | 133
OBUF | 43
Register | 95
DFFPE | 6
DFFCE | 89
LUT | 345
LUT2 | 36
LUT3 | 86
LUT4 | 223
ALU | 32
ALU | 32
SSRAM | 3
RAM16S4 | 3
INV | 5
INV | 5
BSRAM | 4
SDPB | 4

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 400(350 LUTs, 32 ALUs, 3 SSRAMs) / 23040 | 2%
Register | 95 / 23685 | <1%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 95 / 23685 | <1%
BSRAM | 4 / 56 | 8%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
RdClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | RdClk_ibuf/I
WrClk | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | WrClk_ibuf/I
fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n4_s2/O
fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | fifo_inst/n9_s2/O

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | RdClk | 100.0(MHz) | 131.2(MHz) | 12 | TOP
2 | WrClk | 100.0(MHz) | 142.9(MHz) | 11 | TOP
3 | fifo_inst/n4_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP
4 | fifo_inst/n9_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | 2.376
Data Arrival Time | 8.452
Data Required Time | 10.828
From | fifo_inst/Small.rq1_wptr_0_s2
To | fifo_inst/Almost_Empty_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Small.rq1_wptr_0_s2/CLK
1.095 | 0.232 | tC2Q | RF | 8 | fifo_inst/Small.rq1_wptr_0_s2/Q
1.332 | 0.237 | tNET | FF | 2 | fifo_inst/Small.rq1_wptr_0_s12/AD[0]
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[0]
2.086 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/I1
2.641 | 0.555 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
2.878 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
3.331 | 0.453 | tINS | FF | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
3.568 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
3.939 | 0.371 | tINS | FF | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
4.176 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
4.693 | 0.517 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
4.930 | 0.237 | tNET | FF | 2 | fifo_inst/rcnt_sub_3_s/I0
5.479 | 0.549 | tINS | FR | 1 | fifo_inst/rcnt_sub_3_s/COUT
5.479 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
5.514 | 0.035 | tINS | RF | 1 | fifo_inst/rcnt_sub_4_s/COUT
5.514 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_5_s/CIN
5.549 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_5_s/COUT
5.549 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_6_s/CIN
5.584 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_6_s/COUT
5.584 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_7_s/CIN
5.619 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_7_s/COUT
5.619 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_8_s/CIN
5.655 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_8_s/COUT
5.655 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_9_s/CIN
6.125 | 0.470 | tINS | FF | 2 | fifo_inst/rcnt_sub_9_s/SUM
6.362 | 0.237 | tNET | FF | 1 | fifo_inst/arempty_val_s3/I1
6.917 | 0.555 | tINS | FF | 1 | fifo_inst/arempty_val_s3/F
7.154 | 0.237 | tNET | FF | 1 | fifo_inst/arempty_val_s2/I2
7.607 | 0.453 | tINS | FF | 1 | fifo_inst/arempty_val_s2/F
7.844 | 0.237 | tNET | FF | 1 | fifo_inst/arempty_val_s0/I3
8.215 | 0.371 | tINS | FF | 1 | fifo_inst/arempty_val_s0/F
8.452 | 0.237 | tNET | FF | 1 | fifo_inst/Almost_Empty_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Almost_Empty_s0/CLK
10.828 | -0.035 | tSu |  | 1 | fifo_inst/Almost_Empty_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 12
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 4.987, 65.714%; route: 2.370, 31.229%; tC2Q: 0.232, 3.057%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 2

Path Summary:

Slack | 3.001
Data Arrival Time | 7.827
Data Required Time | 10.828
From | fifo_inst/Small.wq2_rptr_7_s0
To | fifo_inst/Almost_Full_s0
Launch Clk | WrClk[R]
Latch Clk | WrClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | WrClk
0.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
0.683 | 0.683 | tINS | RR | 56 | WrClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Small.wq2_rptr_7_s0/CLK
1.095 | 0.232 | tC2Q | RF | 3 | fifo_inst/Small.wq2_rptr_7_s0/Q
1.332 | 0.237 | tNET | FF | 1 | fifo_inst/Small.rcount_w_6_s0/I1
1.887 | 0.555 | tINS | FF | 4 | fifo_inst/Small.rcount_w_6_s0/F
2.124 | 0.237 | tNET | FF | 1 | fifo_inst/Small.rcount_w_4_s0/I2
2.577 | 0.453 | tINS | FF | 3 | fifo_inst/Small.rcount_w_4_s0/F
2.814 | 0.237 | tNET | FF | 1 | fifo_inst/Small.rcount_w_1_s0/I3
3.185 | 0.371 | tINS | FF | 2 | fifo_inst/Small.rcount_w_1_s0/F
3.422 | 0.237 | tNET | FF | 1 | fifo_inst/Small.rcount_w_0_s0/I1
3.977 | 0.555 | tINS | FF | 1 | fifo_inst/Small.rcount_w_0_s0/F
4.214 | 0.237 | tNET | FF | 2 | fifo_inst/wcnt_sub_0_s/I1
4.784 | 0.570 | tINS | FR | 1 | fifo_inst/wcnt_sub_0_s/COUT
4.784 | 0.000 | tNET | RR | 2 | fifo_inst/wcnt_sub_1_s/CIN
4.819 | 0.035 | tINS | RF | 1 | fifo_inst/wcnt_sub_1_s/COUT
4.819 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_2_s/CIN
4.854 | 0.035 | tINS | FF | 1 | fifo_inst/wcnt_sub_2_s/COUT
4.854 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_3_s/CIN
4.889 | 0.035 | tINS | FF | 1 | fifo_inst/wcnt_sub_3_s/COUT
4.889 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_4_s/CIN
4.924 | 0.035 | tINS | FF | 1 | fifo_inst/wcnt_sub_4_s/COUT
4.924 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_5_s/CIN
4.960 | 0.035 | tINS | FF | 1 | fifo_inst/wcnt_sub_5_s/COUT
4.960 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_6_s/CIN
4.995 | 0.035 | tINS | FF | 1 | fifo_inst/wcnt_sub_6_s/COUT
4.995 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_7_s/CIN
5.030 | 0.035 | tINS | FF | 1 | fifo_inst/wcnt_sub_7_s/COUT
5.030 | 0.000 | tNET | FF | 2 | fifo_inst/wcnt_sub_8_s/CIN
5.500 | 0.470 | tINS | FF | 2 | fifo_inst/wcnt_sub_8_s/SUM
5.737 | 0.237 | tNET | FF | 1 | fifo_inst/awfull_val_s2/I1
6.292 | 0.555 | tINS | FF | 1 | fifo_inst/awfull_val_s2/F
6.529 | 0.237 | tNET | FF | 1 | fifo_inst/awfull_val_s1/I2
6.982 | 0.453 | tINS | FF | 1 | fifo_inst/awfull_val_s1/F
7.219 | 0.237 | tNET | FF | 1 | fifo_inst/awfull_val_s0/I3
7.590 | 0.371 | tINS | FF | 1 | fifo_inst/awfull_val_s0/F
7.827 | 0.237 | tNET | FF | 1 | fifo_inst/Almost_Full_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | WrClk
10.000 | 0.000 | tCL | RR | 1 | WrClk_ibuf/I
10.682 | 0.683 | tINS | RR | 56 | WrClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Almost_Full_s0/CLK
10.828 | -0.035 | tSu |  | 1 | fifo_inst/Almost_Full_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 11
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 4.599, 66.042%; route: 2.133, 30.627%; tC2Q: 0.232, 3.331%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 3

Path Summary:

Slack | 4.360
Data Arrival Time | 6.467
Data Required Time | 10.828
From | fifo_inst/Small.rq1_wptr_0_s2
To | fifo_inst/Rnum_12_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Small.rq1_wptr_0_s2/CLK
1.095 | 0.232 | tC2Q | RF | 8 | fifo_inst/Small.rq1_wptr_0_s2/Q
1.332 | 0.237 | tNET | FF | 2 | fifo_inst/Small.rq1_wptr_0_s12/AD[0]
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[0]
2.086 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/I1
2.641 | 0.555 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
2.878 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
3.331 | 0.453 | tINS | FF | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
3.568 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
3.939 | 0.371 | tINS | FF | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
4.176 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
4.693 | 0.517 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
4.930 | 0.237 | tNET | FF | 2 | fifo_inst/rcnt_sub_3_s/I0
5.479 | 0.549 | tINS | FR | 1 | fifo_inst/rcnt_sub_3_s/COUT
5.479 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
5.514 | 0.035 | tINS | RF | 1 | fifo_inst/rcnt_sub_4_s/COUT
5.514 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_5_s/CIN
5.549 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_5_s/COUT
5.549 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_6_s/CIN
5.584 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_6_s/COUT
5.584 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_7_s/CIN
5.619 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_7_s/COUT
5.619 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_8_s/CIN
5.655 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_8_s/COUT
5.655 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_9_s/CIN
5.690 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_9_s/COUT
5.690 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_10_s/CIN
5.725 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_10_s/COUT
5.725 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_11_s/CIN
5.760 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_11_s/COUT
5.760 | 0.000 | tNET | FF | 1 | fifo_inst/rcnt_sub_12_s/CIN
6.230 | 0.470 | tINS | FF | 2 | fifo_inst/rcnt_sub_12_s/SUM
6.467 | 0.237 | tNET | FF | 1 | fifo_inst/Rnum_12_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_12_s0/CLK
10.828 | -0.035 | tSu |  | 1 | fifo_inst/Rnum_12_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 9
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.714, 66.260%; route: 1.659, 29.601%; tC2Q: 0.232, 4.139%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 4

Path Summary:

Slack | 4.396
Data Arrival Time | 6.432
Data Required Time | 10.828
From | fifo_inst/Small.rq1_wptr_0_s2
To | fifo_inst/Rnum_11_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Small.rq1_wptr_0_s2/CLK
1.095 | 0.232 | tC2Q | RF | 8 | fifo_inst/Small.rq1_wptr_0_s2/Q
1.332 | 0.237 | tNET | FF | 2 | fifo_inst/Small.rq1_wptr_0_s12/AD[0]
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[0]
2.086 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/I1
2.641 | 0.555 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
2.878 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
3.331 | 0.453 | tINS | FF | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
3.568 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
3.939 | 0.371 | tINS | FF | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
4.176 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
4.693 | 0.517 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
4.930 | 0.237 | tNET | FF | 2 | fifo_inst/rcnt_sub_3_s/I0
5.479 | 0.549 | tINS | FR | 1 | fifo_inst/rcnt_sub_3_s/COUT
5.479 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
5.514 | 0.035 | tINS | RF | 1 | fifo_inst/rcnt_sub_4_s/COUT
5.514 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_5_s/CIN
5.549 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_5_s/COUT
5.549 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_6_s/CIN
5.584 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_6_s/COUT
5.584 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_7_s/CIN
5.619 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_7_s/COUT
5.619 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_8_s/CIN
5.655 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_8_s/COUT
5.655 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_9_s/CIN
5.690 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_9_s/COUT
5.690 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_10_s/CIN
5.725 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_10_s/COUT
5.725 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_11_s/CIN
6.195 | 0.470 | tINS | FF | 2 | fifo_inst/rcnt_sub_11_s/SUM
6.432 | 0.237 | tNET | FF | 1 | fifo_inst/Rnum_11_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_11_s0/CLK
10.828 | -0.035 | tSu |  | 1 | fifo_inst/Rnum_11_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 9
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.678, 66.046%; route: 1.659, 29.788%; tC2Q: 0.232, 4.166%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%

### Path 5

Path Summary:

Slack | 4.431
Data Arrival Time | 6.397
Data Required Time | 10.828
From | fifo_inst/Small.rq1_wptr_0_s2
To | fifo_inst/Rnum_10_s0
Launch Clk | RdClk[R]
Latch Clk | RdClk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  | RdClk
0.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
0.683 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
0.863 | 0.180 | tNET | RR | 1 | fifo_inst/Small.rq1_wptr_0_s2/CLK
1.095 | 0.232 | tC2Q | RF | 8 | fifo_inst/Small.rq1_wptr_0_s2/Q
1.332 | 0.237 | tNET | FF | 2 | fifo_inst/Small.rq1_wptr_0_s12/AD[0]
1.849 | 0.517 | tINS | FF | 4 | fifo_inst/Small.rq1_wptr_0_s12/DO[0]
2.086 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/I1
2.641 | 0.555 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_10_s2/F
2.878 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_8_s0/I2
3.331 | 0.453 | tINS | FF | 4 | fifo_inst/Small.wcount_r_1_8_s0/F
3.568 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_4_s2/I3
3.939 | 0.371 | tINS | FF | 2 | fifo_inst/Small.wcount_r_1_4_s2/F
4.176 | 0.237 | tNET | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/I0
4.693 | 0.517 | tINS | FF | 1 | fifo_inst/Small.wcount_r_1_3_s1/F
4.930 | 0.237 | tNET | FF | 2 | fifo_inst/rcnt_sub_3_s/I0
5.479 | 0.549 | tINS | FR | 1 | fifo_inst/rcnt_sub_3_s/COUT
5.479 | 0.000 | tNET | RR | 2 | fifo_inst/rcnt_sub_4_s/CIN
5.514 | 0.035 | tINS | RF | 1 | fifo_inst/rcnt_sub_4_s/COUT
5.514 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_5_s/CIN
5.549 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_5_s/COUT
5.549 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_6_s/CIN
5.584 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_6_s/COUT
5.584 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_7_s/CIN
5.619 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_7_s/COUT
5.619 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_8_s/CIN
5.655 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_8_s/COUT
5.655 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_9_s/CIN
5.690 | 0.035 | tINS | FF | 1 | fifo_inst/rcnt_sub_9_s/COUT
5.690 | 0.000 | tNET | FF | 2 | fifo_inst/rcnt_sub_10_s/CIN
6.160 | 0.470 | tINS | FF | 2 | fifo_inst/rcnt_sub_10_s/SUM
6.397 | 0.237 | tNET | FF | 1 | fifo_inst/Rnum_10_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
10.000 | 0.000 |  |  |  | RdClk
10.000 | 0.000 | tCL | RR | 1 | RdClk_ibuf/I
10.682 | 0.683 | tINS | RR | 48 | RdClk_ibuf/O
10.863 | 0.180 | tNET | RR | 1 | fifo_inst/Rnum_10_s0/CLK
10.828 | -0.035 | tSu |  | 1 | fifo_inst/Rnum_10_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 10.000
Logic Level: | 9
Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: | cell: 3.643, 65.831%; route: 1.659, 29.977%; tC2Q: 0.232, 4.192%
Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870%