# Timing Messages

Report Title | Timing Analysis Report
Design File | H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\impl\gwsynthesis\ov5640_ddr3_raw2rgb_tft.vg
Physical Constraints File | H:\01_gaoyun\gao_project\44_ov5640_ddr3_raw2rgb_tft_hdmi\ov5640_ddr3_raw2rgb_tft\src\ov5640_ddr3_raw2rgb_tft.cst
Timing Constraint File | ---
Version | V1.9.9 Beta-5
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Fri Oct 13 10:05:09 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.85V -40C ES
Hold Delay Model | Fast 0.95V 100C ES
Numbers of Paths Analyzed | 42777
Numbers of Endpoints Analyzed | 37235
Numbers of Falling Endpoints | 64
Numbers of Setup Violated Endpoints | 9466
Numbers of Hold Violated Endpoints | 21

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk50m | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | clk50m_ibuf/I
camera_pclk | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  | camera_pclk_ibuf/I
RAW2RGB/clk_ce | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  | RAW2RGB/DCE/CLKOUT
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 41.250 | 24.242 | 0.000 | 20.625 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT1
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT2
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 30.000 | 33.333 | 0.000 | 15.000 | clk50m_ibuf/I | clk50m | Gowin_PLL/PLLA_inst/CLKOUT3
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | Gowin_PLL/PLLA_inst/CLKOUT2 | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | camera_pclk | 100.000(MHz) | 100.395(MHz) | 7 | TOP
2 | RAW2RGB/clk_ce | 100.000(MHz) | 76.252(MHz) | 4 | TOP
3 | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 182.909(MHz) | 4 | TOP
4 | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | 200.000(MHz) | 2016.128(MHz) | 1 | TOP
5 | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | 33.333(MHz) | 55.017(MHz) | 10 | TOP
6 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.000(MHz) | 101.340(MHz) | 2 | TOP

#### No timing paths to get frequency of clk50m!

#### No timing paths to get frequency of Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
clk50m | Setup | 0.000 | 0
clk50m | Hold | 0.000 | 0
camera_pclk | Setup | 0.000 | 0
camera_pclk | Hold | 0.000 | 0
RAW2RGB/clk_ce | Setup | -1176.182 | 1224
RAW2RGB/clk_ce | Hold | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Setup | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT1.default_gen_clk | Hold | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | Setup | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk | Hold | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | Setup | 0.000 | 0
Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk | Hold | 0.000 | 0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Setup | 0.000 | 0
ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -17.708 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_926_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.692 | 26.923
2 | -17.550 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_894_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.718 | 26.739
3 | -17.543 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_830_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.711 | 26.739
4 | -17.361 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_734_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.714 | 26.554
5 | -17.132 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_446_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.723 | 26.316
6 | -16.809 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_990_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.700 | 26.011
7 | -16.729 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_510_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.740 | 25.897
8 | -16.729 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_478_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.740 | 25.897
9 | -16.720 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_574_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.731 | 25.897
10 | -16.720 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_382_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.731 | 25.897
11 | -16.720 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_254_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.731 | 25.897
12 | -16.687 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_606_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.749 | 25.846
13 | -16.670 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_958_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.723 | 25.854
14 | -16.661 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_766_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.714 | 25.854
15 | -16.646 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_862_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.733 | 25.821
16 | -16.629 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_638_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.723 | 25.813
17 | -16.629 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_787_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.685 | 25.852
18 | -16.629 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_595_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.685 | 25.852
19 | -16.629 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_531_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.685 | 25.852
20 | -16.620 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_915_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.675 | 25.852
21 | -16.620 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_723_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.675 | 25.852
22 | -16.620 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_659_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.675 | 25.852
23 | -16.602 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_798_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.740 | 25.769
24 | -16.494 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_286_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.740 | 25.662
25 | -16.494 | disp_driver/Disp_DE_s0/Q | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_158_G[1]_s0/D | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | RAW2RGB/clk_ce:[R] | 10.000 | 0.740 | 25.662

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -0.534 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.104 | 0.416
2 | -0.516 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.104 | 0.599
3 | -0.516 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.104 | 0.599
4 | -0.515 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.102 | 0.599
5 | -0.514 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.104 | 0.601
6 | -0.507 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.102 | 0.606
7 | -0.485 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.684 | 0.296
8 | -0.415 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.104 | 0.700
9 | -0.411 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.101 | 0.536
10 | -0.409 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.104 | 0.706
11 | -0.393 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | camera_pclk:[R] | 0.000 | -1.101 | 0.719
12 | -0.385 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[3] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.685 | 0.397
13 | -0.385 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[1] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.685 | 0.397
14 | -0.384 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[1] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.684 | 0.397
15 | -0.375 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[2] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.694 | 0.416
16 | -0.370 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.689 | 0.416
17 | -0.360 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[1] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.690 | 0.428
18 | -0.281 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[3] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.694 | 0.510
19 | -0.278 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.690 | 0.510
20 | -0.159 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[2] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.686 | 0.624
21 | -0.047 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_0_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/D | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.692 | 0.681
22 | 0.004 | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_4_s0/Q | RAW2RGB/r1_RAW_Data_s_4_s0/D | RAW2RGB/clk_ce:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.694 | 0.734
23 | 0.031 | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_6_s0/Q | RAW2RGB/r1_RAW_Data_s_6_s0/D | RAW2RGB/clk_ce:[R] | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R] | 0.000 | -0.657 | 0.725
24 | 0.072 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.018 | 0.304
25 | 0.078 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[22] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.021 | 0.306

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -1.727 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
2 | -1.727 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
3 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
4 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
5 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
6 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
7 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
8 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
9 | -1.391 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | 2.500 | 0.670 | 3.035
10 | 0.767 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
11 | 0.767 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
12 | 1.103 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
13 | 1.103 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
14 | 1.103 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
15 | 1.103 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
16 | 1.103 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
17 | 1.103 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 5.000 | 0.674 | 3.035
18 | 15.790 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.641 | 3.035
19 | 15.809 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.623 | 3.035
20 | 16.135 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.641 | 3.035
21 | 16.135 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.641 | 3.035
22 | 16.145 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.632 | 3.035
23 | 16.145 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.632 | 3.035
24 | 16.154 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.623 | 3.035
25 | 16.154 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 20.000 | 0.623 | 3.035

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 1.135 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.161 | 1.485
2 | 1.135 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.161 | 1.485
3 | 1.224 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.072 | 1.485
4 | 1.224 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.072 | 1.485
5 | 1.224 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.072 | 1.485
6 | 1.224 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.072 | 1.485
7 | 1.224 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | -0.072 | 1.485
8 | 1.503 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | 0.207 | 1.485
9 | 1.503 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | 0.207 | 1.485
10 | 1.503 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | 0.207 | 1.485
11 | 1.503 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | 0.207 | 1.485
12 | 1.503 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | 0.207 | 1.485
13 | 1.503 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R] | 0.000 | 0.207 | 1.485
14 | 1.936 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.639 | 1.485
15 | 1.936 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.639 | 1.485
16 | 1.936 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.639 | 1.485
17 | 1.941 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.644 | 1.485
18 | 1.941 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.644 | 1.485
19 | 1.941 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.644 | 1.485
20 | 3.610 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | -2.500 | -0.188 | 1.485
21 | 3.610 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | -2.500 | -0.188 | 1.485
22 | 3.711 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | -2.500 | -0.088 | 1.485
23 | 3.711 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | -2.500 | -0.088 | 1.485
24 | 3.711 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | -2.500 | -0.088 | 1.485
25 | 3.711 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R] | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F] | -2.500 | -0.088 | 1.485

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 3.146 | 4.146 | 1.000 | High Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s
2 | 3.151 | 4.151 | 1.000 | High Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s
3 | 3.151 | 4.151 | 1.000 | High Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s
4 | 3.155 | 4.155 | 1.000 | High Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s
5 | 3.177 | 4.177 | 1.000 | Low Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s
6 | 3.181 | 4.181 | 1.000 | Low Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s
7 | 3.181 | 4.181 | 1.000 | Low Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s
8 | 3.186 | 4.186 | 1.000 | Low Pulse Width | camera_pclk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s
9 | 3.887 | 4.137 | 0.250 | High Pulse Width | camera_pclk | DVP_Capture/r_Data_6_s0
10 | 3.887 | 4.137 | 0.250 | High Pulse Width | camera_pclk | DVP_Capture/r_Data_7_s0

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -17.708
Data Arrival Time | 28.508
Data Required Time | 10.800
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_926_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
28.508 | 11.339 | tNET | FF | 1 | R8C89[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_926_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.893 | 0.893 | tNET | RR | 1 | R8C89[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_926_G[1]_s0/CLK
10.858 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_926_G[1]_s0
10.800 | -0.058 | tSu |  | 1 | R8C89[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_926_G[1]_s0

Path Statistics:

Clock Skew | -0.692
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.251%; route: 23.781, 88.328%; tC2Q: 0.382, 1.421%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.893, 100.000%

### Path2

Path Summary:

Slack | -17.550
Data Arrival Time | 28.325
Data Required Time | 10.774
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_894_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
28.325 | 11.155 | tNET | FF | 1 | R9C87[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_894_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.867 | 0.867 | tNET | RR | 1 | R9C87[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_894_G[1]_s0/CLK
10.832 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_894_G[1]_s0
10.774 | -0.058 | tSu |  | 1 | R9C87[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_894_G[1]_s0

Path Statistics:

Clock Skew | -0.718
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.322%; route: 23.597, 88.248%; tC2Q: 0.382, 1.430%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.867, 100.000%

### Path3

Path Summary:

Slack | -17.543
Data Arrival Time | 28.325
Data Required Time | 10.782
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_830_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
28.325 | 11.155 | tNET | FF | 1 | R8C87[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_830_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.874 | 0.874 | tNET | RR | 1 | R8C87[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_830_G[1]_s0/CLK
10.839 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_830_G[1]_s0
10.782 | -0.058 | tSu |  | 1 | R8C87[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_830_G[1]_s0

Path Statistics:

Clock Skew | -0.711
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.322%; route: 23.597, 88.248%; tC2Q: 0.382, 1.430%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.874, 100.000%

### Path4

Path Summary:

Slack | -17.361
Data Arrival Time | 28.140
Data Required Time | 10.779
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_734_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
28.140 | 10.970 | tNET | FF | 1 | R11C85[3][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_734_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.871 | 0.871 | tNET | RR | 1 | R11C85[3][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_734_G[1]_s0/CLK
10.836 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_734_G[1]_s0
10.779 | -0.058 | tSu |  | 1 | R11C85[3][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_734_G[1]_s0

Path Statistics:

Clock Skew | -0.714
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.394%; route: 23.412, 88.166%; tC2Q: 0.382, 1.440%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.871, 100.000%

### Path5

Path Summary:

Slack | -17.132
Data Arrival Time | 27.901
Data Required Time | 10.769
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_446_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.901 | 10.731 | tNET | FF | 1 | R11C86[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_446_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.862 | 0.862 | tNET | RR | 1 | R11C86[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_446_G[1]_s0/CLK
10.827 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_446_G[1]_s0
10.769 | -0.058 | tSu |  | 1 | R11C86[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_446_G[1]_s0

Path Statistics:

Clock Skew | -0.723
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.488%; route: 23.173, 88.058%; tC2Q: 0.382, 1.454%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000%

### Path6

Path Summary:

Slack | -16.809
Data Arrival Time | 27.596
Data Required Time | 10.787
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_990_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.197 | 0.262 | tINS | RR | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.596 | 10.399 | tNET | RR | 1 | R9C85[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_990_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.886 | 0.886 | tNET | RR | 1 | R9C85[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_990_G[1]_s0/CLK
10.851 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_990_G[1]_s0
10.787 | -0.064 | tSu |  | 1 | R9C85[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_990_G[1]_s0

Path Statistics:

Clock Skew | -0.700
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.788, 10.717%; route: 22.841, 87.813%; tC2Q: 0.382, 1.471%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.886, 100.000%

### Path7

Path Summary:

Slack | -16.729
Data Arrival Time | 27.482
Data Required Time | 10.753
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_510_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.482 | 10.313 | tNET | FF | 1 | R12C88[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_510_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.845 | 0.845 | tNET | RR | 1 | R12C88[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_510_G[1]_s0/CLK
10.810 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_510_G[1]_s0
10.753 | -0.058 | tSu |  | 1 | R12C88[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_510_G[1]_s0

Path Statistics:

Clock Skew | -0.740
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.658%; route: 22.754, 87.865%; tC2Q: 0.382, 1.477%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000%

### Path8

Path Summary:

Slack | -16.729
Data Arrival Time | 27.482
Data Required Time | 10.753
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_478_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.482 | 10.313 | tNET | FF | 1 | R12C88[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_478_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.845 | 0.845 | tNET | RR | 1 | R12C88[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_478_G[1]_s0/CLK
10.810 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_478_G[1]_s0
10.753 | -0.058 | tSu |  | 1 | R12C88[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_478_G[1]_s0

Path Statistics:

Clock Skew | -0.740
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.658%; route: 22.754, 87.865%; tC2Q: 0.382, 1.477%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000%

### Path9

Path Summary:

Slack | -16.720
Data Arrival Time | 27.482
Data Required Time | 10.762
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_574_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.482 | 10.313 | tNET | FF | 1 | R12C89[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_574_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.855 | 0.855 | tNET | RR | 1 | R12C89[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_574_G[1]_s0/CLK
10.820 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_574_G[1]_s0
10.762 | -0.058 | tSu |  | 1 | R12C89[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_574_G[1]_s0

Path Statistics:

Clock Skew | -0.731
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.658%; route: 22.754, 87.865%; tC2Q: 0.382, 1.477%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.855, 100.000%

### Path10

Path Summary:

Slack | -16.720
Data Arrival Time | 27.482
Data Required Time | 10.762
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_382_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.482 | 10.313 | tNET | FF | 1 | R12C89[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_382_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.855 | 0.855 | tNET | RR | 1 | R12C89[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_382_G[1]_s0/CLK
10.820 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_382_G[1]_s0
10.762 | -0.058 | tSu |  | 1 | R12C89[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_382_G[1]_s0

Path Statistics:

Clock Skew | -0.731
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.658%; route: 22.754, 87.865%; tC2Q: 0.382, 1.477%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.855, 100.000%

### Path11

Path Summary:

Slack | -16.720
Data Arrival Time | 27.482
Data Required Time | 10.762
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_254_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.482 | 10.313 | tNET | FF | 1 | R12C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_254_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.855 | 0.855 | tNET | RR | 1 | R12C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_254_G[1]_s0/CLK
10.820 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_254_G[1]_s0
10.762 | -0.058 | tSu |  | 1 | R12C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_254_G[1]_s0

Path Statistics:

Clock Skew | -0.731
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.658%; route: 22.754, 87.865%; tC2Q: 0.382, 1.477%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.855, 100.000%

### Path12

Path Summary:

Slack | -16.687
Data Arrival Time | 27.431
Data Required Time | 10.743
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_606_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.431 | 10.261 | tNET | FF | 1 | R12C91[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_606_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.836 | 0.836 | tNET | RR | 1 | R12C91[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_606_G[1]_s0/CLK
10.801 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_606_G[1]_s0
10.743 | -0.058 | tSu |  | 1 | R12C91[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_606_G[1]_s0

Path Statistics:

Clock Skew | -0.749
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.679%; route: 22.703, 87.841%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.836, 100.000%

### Path13

Path Summary:

Slack | -16.670
Data Arrival Time | 27.440
Data Required Time | 10.769
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_958_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.440 | 10.270 | tNET | FF | 1 | R11C88[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_958_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.862 | 0.862 | tNET | RR | 1 | R11C88[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_958_G[1]_s0/CLK
10.827 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_958_G[1]_s0
10.769 | -0.058 | tSu |  | 1 | R11C88[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_958_G[1]_s0

Path Statistics:

Clock Skew | -0.723
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.675%; route: 22.712, 87.845%; tC2Q: 0.382, 1.479%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000%

### Path14

Path Summary:

Slack | -16.661
Data Arrival Time | 27.440
Data Required Time | 10.779
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_766_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.440 | 10.270 | tNET | FF | 1 | R11C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_766_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.871 | 0.871 | tNET | RR | 1 | R11C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_766_G[1]_s0/CLK
10.836 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_766_G[1]_s0
10.779 | -0.058 | tSu |  | 1 | R11C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_766_G[1]_s0

Path Statistics:

Clock Skew | -0.714
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.675%; route: 22.712, 87.845%; tC2Q: 0.382, 1.479%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.871, 100.000%

### Path15

Path Summary:

Slack | -16.646
Data Arrival Time | 27.406
Data Required Time | 10.760
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_862_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.406 | 10.236 | tNET | FF | 1 | R11C91[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_862_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.852 | 0.852 | tNET | RR | 1 | R11C91[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_862_G[1]_s0/CLK
10.818 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_862_G[1]_s0
10.760 | -0.058 | tSu |  | 1 | R11C91[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_862_G[1]_s0

Path Statistics:

Clock Skew | -0.733
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.689%; route: 22.678, 87.829%; tC2Q: 0.382, 1.481%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.852, 100.000%

### Path16

Path Summary:

Slack | -16.629
Data Arrival Time | 27.398
Data Required Time | 10.769
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_638_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.398 | 10.229 | tNET | FF | 1 | R11C84[3][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_638_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.862 | 0.862 | tNET | RR | 1 | R11C84[3][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_638_G[1]_s0/CLK
10.827 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_638_G[1]_s0
10.769 | -0.058 | tSu |  | 1 | R11C84[3][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_638_G[1]_s0

Path Statistics:

Clock Skew | -0.723
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.692%; route: 22.671, 87.826%; tC2Q: 0.382, 1.482%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.862, 100.000%

### Path17

Path Summary:

Slack | -16.629
Data Arrival Time | 27.437
Data Required Time | 10.808
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_787_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.437 | 10.267 | tNET | FF | 1 | R21C90[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_787_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.901 | 0.901 | tNET | RR | 1 | R21C90[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_787_G[1]_s0/CLK
10.866 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_787_G[1]_s0
10.808 | -0.058 | tSu |  | 1 | R21C90[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_787_G[1]_s0

Path Statistics:

Clock Skew | -0.685
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.676%; route: 22.709, 87.844%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.901, 100.000%

### Path18

Path Summary:

Slack | -16.629
Data Arrival Time | 27.437
Data Required Time | 10.808
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_595_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.437 | 10.267 | tNET | FF | 1 | R21C90[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_595_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.901 | 0.901 | tNET | RR | 1 | R21C90[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_595_G[1]_s0/CLK
10.866 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_595_G[1]_s0
10.808 | -0.058 | tSu |  | 1 | R21C90[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_595_G[1]_s0

Path Statistics:

Clock Skew | -0.685
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.676%; route: 22.709, 87.844%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.901, 100.000%

### Path19

Path Summary:

Slack | -16.629
Data Arrival Time | 27.437
Data Required Time | 10.808
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_531_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.437 | 10.267 | tNET | FF | 1 | R21C90[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_531_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.901 | 0.901 | tNET | RR | 1 | R21C90[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_531_G[1]_s0/CLK
10.866 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_531_G[1]_s0
10.808 | -0.058 | tSu |  | 1 | R21C90[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_531_G[1]_s0

Path Statistics:

Clock Skew | -0.685
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.676%; route: 22.709, 87.844%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.901, 100.000%

### Path20

Path Summary:

Slack | -16.620
Data Arrival Time | 27.437
Data Required Time | 10.818
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_915_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.437 | 10.267 | tNET | FF | 1 | R21C89[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_915_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.910 | 0.910 | tNET | RR | 1 | R21C89[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_915_G[1]_s0/CLK
10.875 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_915_G[1]_s0
10.818 | -0.058 | tSu |  | 1 | R21C89[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_915_G[1]_s0

Path Statistics:

Clock Skew | -0.675
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.676%; route: 22.709, 87.844%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.910, 100.000%

### Path21

Path Summary:

Slack | -16.620
Data Arrival Time | 27.437
Data Required Time | 10.818
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_723_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.437 | 10.267 | tNET | FF | 1 | R21C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_723_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.910 | 0.910 | tNET | RR | 1 | R21C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_723_G[1]_s0/CLK
10.875 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_723_G[1]_s0
10.818 | -0.058 | tSu |  | 1 | R21C89[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_723_G[1]_s0

Path Statistics:

Clock Skew | -0.675
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.676%; route: 22.709, 87.844%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.910, 100.000%

### Path22

Path Summary:

Slack | -16.620
Data Arrival Time | 27.437
Data Required Time | 10.818
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_659_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.437 | 10.267 | tNET | FF | 1 | R21C89[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_659_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.910 | 0.910 | tNET | RR | 1 | R21C89[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_659_G[1]_s0/CLK
10.875 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_659_G[1]_s0
10.818 | -0.058 | tSu |  | 1 | R21C89[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_659_G[1]_s0

Path Statistics:

Clock Skew | -0.675
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.676%; route: 22.709, 87.844%; tC2Q: 0.382, 1.480%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.910, 100.000%

### Path23

Path Summary:

Slack | -16.602
Data Arrival Time | 27.355
Data Required Time | 10.753
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_798_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.355 | 10.185 | tNET | FF | 1 | R12C90[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_798_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.845 | 0.845 | tNET | RR | 1 | R12C90[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_798_G[1]_s0/CLK
10.810 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_798_G[1]_s0
10.753 | -0.058 | tSu |  | 1 | R12C90[2][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_798_G[1]_s0

Path Statistics:

Clock Skew | -0.740
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.710%; route: 22.627, 87.805%; tC2Q: 0.382, 1.484%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000%

### Path24

Path Summary:

Slack | -16.494
Data Arrival Time | 27.247
Data Required Time | 10.753
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_286_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.247 | 10.078 | tNET | FF | 1 | R12C90[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_286_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.845 | 0.845 | tNET | RR | 1 | R12C90[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_286_G[1]_s0/CLK
10.810 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_286_G[1]_s0
10.753 | -0.058 | tSu |  | 1 | R12C90[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_286_G[1]_s0

Path Statistics:

Clock Skew | -0.740
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.755%; route: 22.519, 87.754%; tC2Q: 0.382, 1.491%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000%

### Path25

Path Summary:

Slack | -16.494
Data Arrival Time | 27.247
Data Required Time | 10.753
From | disp_driver/Disp_DE_s0
To | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_158_G[1]_s0
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]
Latch Clk | RAW2RGB/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
0.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
1.585 | 0.903 | tNET | RR | 1 | R2C79[1][A] | disp_driver/Disp_DE_s0/CLK
1.968 | 0.382 | tC2Q | RR | 22 | R2C79[1][A] | disp_driver/Disp_DE_s0/Q
8.679 | 6.711 | tNET | RR | 1 | R29C12[3][B] | n125_s0/I1
9.094 | 0.415 | tINS | RR | 38 | R29C12[3][B] | n125_s0/F
10.527 | 1.433 | tNET | RR | 1 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/I1
11.043 | 0.516 | tINS | RR | 8 | R34C2[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_13_s8/F
11.918 | 0.875 | tNET | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/I2
12.445 | 0.526 | tINS | RR | 1 | R35C5[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s4/F
12.772 | 0.327 | tNET | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/I0
13.187 | 0.415 | tINS | RR | 1 | R36C5[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Q_d_1_s1/F
13.570 | 0.382 | tNET | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/I3
14.086 | 0.516 | tINS | RR | 1 | R33C5[2][B] | RAW_Data_1_s2/F
14.086 | 0.000 | tNET | RR | 1 | R33C5[2][A] | RAW_Data_1_s0/I1
14.222 | 0.136 | tINS | RR | 2 | R33C5[2][A] | RAW_Data_1_s0/O
16.935 | 2.713 | tNET | RR | 1 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/I1
17.170 | 0.235 | tINS | RF | 1024 | R34C61[2][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/n175_s2/F
27.247 | 10.078 | tNET | FF | 1 | R12C90[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_158_G[1]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
10.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
10.845 | 0.845 | tNET | RR | 1 | R12C90[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_158_G[1]_s0/CLK
10.810 | -0.035 | tUnc |  |  |  | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_158_G[1]_s0
10.753 | -0.058 | tSu |  | 1 | R12C90[1][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/mem_mem_RAMREG_158_G[1]_s0

Path Statistics:

Clock Skew | -0.740
Setup Relationship | 10.000
Logic Level | 7
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.903, 100.000%
Arrival Data Path Delay | cell: 2.760, 10.755%; route: 22.519, 87.754%; tC2Q: 0.382, 1.491%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.845, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -0.534
Data Arrival Time | 0.791
Data Required Time | 1.325
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.374 | 0.374 | tNET | RR | 1 | R35C12[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0/CLK
0.554 | 0.180 | tC2Q | RR | 1 | R35C12[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_0_s0/Q
0.791 | 0.236 | tNET | RR | 1 | R34C11[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.478 | 0.803 | tNET | RR | 1 | R34C11[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0/CLK
1.513 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0
1.325 | -0.189 | tHld |  | 1 | R34C11[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_0_s0

Path Statistics:

Clock Skew | 1.104
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay | cell: 0.675, 45.694%; route: 0.803, 54.306%

### Path2

Path Summary:

Slack | -0.516
Data Arrival Time | 0.968
Data Required Time | 1.485
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 | 0.369 | tNET | RR | 1 | R35C13[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0/CLK
0.549 | 0.180 | tC2Q | RR | 1 | R35C13[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_7_s0/Q
0.968 | 0.419 | tNET | RR | 1 | R34C12[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.473 | 0.798 | tNET | RR | 1 | R34C12[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0/CLK
1.508 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0
1.485 | -0.024 | tHld |  | 1 | R34C12[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_7_s0

Path Statistics:

Clock Skew | 1.104
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.419, 69.937%; tC2Q: 0.180, 30.063%
Required Clock Path Delay | cell: 0.675, 45.849%; route: 0.798, 54.151%

### Path3

Path Summary:

Slack | -0.516
Data Arrival Time | 0.967
Data Required Time | 1.483
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.368 | 0.368 | tNET | RR | 1 | R34C11[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0/CLK
0.548 | 0.180 | tC2Q | RR | 1 | R34C11[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_5_s0/Q
0.967 | 0.419 | tNET | RR | 1 | R33C12[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.472 | 0.796 | tNET | RR | 1 | R33C12[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0/CLK
1.507 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0
1.483 | -0.024 | tHld |  | 1 | R33C12[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_5_s0

Path Statistics:

Clock Skew | 1.104
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.419, 69.937%; tC2Q: 0.180, 30.063%
Required Clock Path Delay | cell: 0.675, 45.898%; route: 0.796, 54.102%

### Path4

Path Summary:

Slack | -0.515
Data Arrival Time | 0.975
Data Required Time | 1.490
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.376 | 0.376 | tNET | RR | 1 | R36C12[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/CLK
0.556 | 0.180 | tC2Q | RR | 1 | R36C12[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/Q
0.975 | 0.419 | tNET | RR | 1 | R34C11[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.478 | 0.803 | tNET | RR | 1 | R34C11[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/CLK
1.513 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0
1.490 | -0.024 | tHld |  | 1 | R34C11[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0

Path Statistics:

Clock Skew | 1.102
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.376, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.419, 69.937%; tC2Q: 0.180, 30.063%
Required Clock Path Delay | cell: 0.675, 45.694%; route: 0.803, 54.306%

### Path5

Path Summary:

Slack | -0.514
Data Arrival Time | 0.964
Data Required Time | 1.478
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.363 | 0.363 | tNET | RR | 1 | R34C14[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0/CLK
0.543 | 0.180 | tC2Q | RR | 1 | R34C14[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_8_s0/Q
0.964 | 0.421 | tNET | RR | 1 | R33C13[3][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.467 | 0.791 | tNET | RR | 1 | R33C13[3][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0/CLK
1.502 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0
1.478 | -0.024 | tHld |  | 1 | R33C13[3][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_8_s0

Path Statistics:

Clock Skew | 1.104
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.421, 70.062%; tC2Q: 0.180, 29.938%
Required Clock Path Delay | cell: 0.675, 46.054%; route: 0.791, 53.946%

### Path6

Path Summary:

Slack | -0.507
Data Arrival Time | 0.972
Data Required Time | 1.480
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.366 | 0.366 | tNET | RR | 1 | R36C14[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0/CLK
0.546 | 0.180 | tC2Q | RR | 1 | R36C14[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_1_s0/Q
0.972 | 0.426 | tNET | RR | 1 | R34C13[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.468 | 0.793 | tNET | RR | 1 | R34C13[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0/CLK
1.503 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0
1.480 | -0.024 | tHld |  | 1 | R34C13[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_1_s0

Path Statistics:

Clock Skew | 1.102
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.426, 70.309%; tC2Q: 0.180, 29.691%
Required Clock Path Delay | cell: 0.675, 46.005%; route: 0.793, 53.995%

### Path7

Path Summary:

Slack | -0.485
Data Arrival Time | 60.667
Data Required Time | 61.152
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.371 | 0.371 | tNET | RR | 1 | R33C8[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/CLK
60.551 | 0.180 | tC2Q | RR | 1 | R33C8[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_4_s0/Q
60.667 | 0.116 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[0]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.055 | 0.373 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
61.090 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
61.152 | 0.063 | tHld |  | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew | 0.684
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.116, 39.241%; tC2Q: 0.180, 60.759%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.373, 100.000%

### Path8

Path Summary:

Slack | -0.415
Data Arrival Time | 1.069
Data Required Time | 1.485
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 | 0.369 | tNET | RR | 1 | R35C13[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0/CLK
0.549 | 0.180 | tC2Q | RR | 1 | R35C13[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_6_s0/Q
1.069 | 0.520 | tNET | RR | 1 | R34C12[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.473 | 0.798 | tNET | RR | 1 | R34C12[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0/CLK
1.508 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0
1.485 | -0.024 | tHld |  | 1 | R34C12[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_6_s0

Path Statistics:

Clock Skew | 1.104
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.520, 74.286%; tC2Q: 0.180, 25.714%
Required Clock Path Delay | cell: 0.675, 45.849%; route: 0.798, 54.151%

### Path9

Path Summary:

Slack | -0.411
Data Arrival Time | 0.907
Data Required Time | 1.318
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.371 | 0.371 | tNET | RR | 1 | R36C13[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/CLK
0.551 | 0.180 | tC2Q | RR | 1 | R36C13[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/Q
0.907 | 0.356 | tNET | RR | 1 | R33C12[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.472 | 0.796 | tNET | RR | 1 | R33C12[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/CLK
1.507 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0
1.318 | -0.189 | tHld |  | 1 | R33C12[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0

Path Statistics:

Clock Skew | 1.101
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.356, 66.434%; tC2Q: 0.180, 33.566%
Required Clock Path Delay | cell: 0.675, 45.898%; route: 0.796, 54.102%

### Path10

Path Summary:

Slack | -0.409
Data Arrival Time | 1.069
Data Required Time | 1.478
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.363 | 0.363 | tNET | RR | 1 | R34C14[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0/CLK
0.543 | 0.180 | tC2Q | RR | 4 | R34C14[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/rbin_num_9_s0/Q
1.069 | 0.526 | tNET | RR | 1 | R33C13[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.467 | 0.791 | tNET | RR | 1 | R33C13[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0/CLK
1.502 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0
1.478 | -0.024 | tHld |  | 1 | R33C13[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_9_s0

Path Statistics:

Clock Skew | 1.104
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.526, 74.513%; tC2Q: 0.180, 25.487%
Required Clock Path Delay | cell: 0.675, 46.054%; route: 0.791, 53.946%

### Path11

Path Summary:

Slack | -0.393
Data Arrival Time | 1.090
Data Required Time | 1.483
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | camera_pclk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.371 | 0.371 | tNET | RR | 1 | R36C13[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0/CLK
0.551 | 0.180 | tC2Q | RR | 1 | R36C13[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_2_s0/Q
1.090 | 0.539 | tNET | RR | 1 | R33C12[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | 1 | IOR18[B] | camera_pclk_ibuf/I
0.675 | 0.675 | tINS | RR | 100 | IOR18[B] | camera_pclk_ibuf/O
1.472 | 0.796 | tNET | RR | 1 | R33C12[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0/CLK
1.507 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0
1.483 | -0.024 | tHld |  | 1 | R33C12[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_2_s0

Path Statistics:

Clock Skew | 1.101
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.539, 74.957%; tC2Q: 0.180, 25.043%
Required Clock Path Delay | cell: 0.675, 45.898%; route: 0.796, 54.102%

### Path12

Path Summary:

Slack | -0.385
Data Arrival Time | 60.764
Data Required Time | 61.149
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.366 | 0.366 | tNET | RR | 1 | R33C9[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/CLK
60.546 | 0.180 | tC2Q | RR | 1 | R33C9[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_3_s0/Q
60.764 | 0.217 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[3]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.051 | 0.369 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
61.086 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
61.149 | 0.063 | tHld |  | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew | 0.685
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%

### Path13

Path Summary:

Slack | -0.385
Data Arrival Time | 60.764
Data Required Time | 61.149
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.366 | 0.366 | tNET | RR | 1 | R33C9[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/CLK
60.546 | 0.180 | tC2Q | RR | 1 | R33C9[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_1_s0/Q
60.764 | 0.217 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[1]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.051 | 0.369 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
61.086 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
61.149 | 0.063 | tHld |  | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew | 0.685
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%

### Path14

Path Summary:

Slack | -0.384
Data Arrival Time | 60.769
Data Required Time | 61.152
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.371 | 0.371 | tNET | RR | 1 | R33C8[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/CLK
60.551 | 0.180 | tC2Q | RR | 1 | R33C8[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_5_s0/Q
60.769 | 0.217 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[1]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.055 | 0.373 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
61.090 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
61.152 | 0.063 | tHld |  | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew | 0.684
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.371, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.217, 54.717%; tC2Q: 0.180, 45.283%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.373, 100.000%

### Path15

Path Summary:

Slack | -0.375
Data Arrival Time | 60.778
Data Required Time | 61.152
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.361 | 0.361 | tNET | RR | 1 | R33C10[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/CLK
60.541 | 0.180 | tC2Q | RR | 1 | R33C10[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_6_s0/Q
60.778 | 0.236 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[2]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.055 | 0.373 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
61.090 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
61.152 | 0.063 | tHld |  | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew | 0.694
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.373, 100.000%

### Path16

Path Summary:

Slack | -0.370
Data Arrival Time | 60.784
Data Required Time | 61.154
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.368 | 0.368 | tNET | RR | 1 | R34C7[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/CLK
60.548 | 0.180 | tC2Q | RR | 1 | R34C7[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_8_s0/Q
60.784 | 0.236 | tNET | RR | 1 | R35C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[0]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.056 | 0.374 | tNET | RR | 1 | R35C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/CLK
61.091 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
61.154 | 0.063 | tHld |  | 1 | R35C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12

Path Statistics:

Clock Skew | 0.689
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 56.757%; tC2Q: 0.180, 43.243%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000%

### Path17

Path Summary:

Slack | -0.360
Data Arrival Time | 60.794
Data Required Time | 61.154
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.366 | 0.366 | tNET | RR | 1 | R33C9[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/CLK
60.546 | 0.180 | tC2Q | RR | 6 | R33C9[1][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_9_s0/Q
60.794 | 0.248 | tNET | RR | 1 | R35C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/DI[1]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.056 | 0.374 | tNET | RR | 1 | R35C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12/CLK
61.091 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12
61.154 | 0.063 | tHld |  | 1 | R35C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s12

Path Statistics:

Clock Skew | 0.690
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.248, 57.895%; tC2Q: 0.180, 42.105%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.374, 100.000%

### Path18

Path Summary:

Slack | -0.281
Data Arrival Time | 60.871
Data Required Time | 61.152
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.361 | 0.361 | tNET | RR | 1 | R33C10[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/CLK
60.541 | 0.180 | tC2Q | RR | 1 | R33C10[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_7_s0/Q
60.871 | 0.330 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/DI[3]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.055 | 0.373 | tNET | RR | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10/CLK
61.090 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10
61.152 | 0.063 | tHld |  | 1 | R34C8 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s10

Path Statistics:

Clock Skew | 0.694
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.330, 64.706%; tC2Q: 0.180, 35.294%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.373, 100.000%

### Path19

Path Summary:

Slack | -0.278
Data Arrival Time | 60.871
Data Required Time | 61.149
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.361 | 0.361 | tNET | RR | 1 | R33C10[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/CLK
60.541 | 0.180 | tC2Q | RR | 1 | R33C10[2][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_0_s0/Q
60.871 | 0.330 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[0]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.051 | 0.369 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
61.086 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
61.149 | 0.063 | tHld |  | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew | 0.690
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.361, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.330, 64.706%; tC2Q: 0.180, 35.294%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%

### Path20

Path Summary:

Slack | -0.159
Data Arrival Time | 60.990
Data Required Time | 61.149
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.366 | 0.366 | tNET | RR | 1 | R36C6[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/CLK
60.546 | 0.180 | tC2Q | RR | 1 | R36C6[3][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wptr_2_s0/Q
60.990 | 0.444 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/DI[2]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
60.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
61.051 | 0.369 | tNET | RR | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8/CLK
61.086 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8
61.149 | 0.063 | tHld |  | 1 | R35C9 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rq1_wptr_0_s8

Path Statistics:

Clock Skew | 0.686
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.366, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.444, 71.142%; tC2Q: 0.180, 28.858%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%

### Path21

Path Summary:

Slack | -0.047
Data Arrival Time | 1.033
Data Required Time | 1.080
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_0_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.351 | 0.351 | tNET | RR | 1 | R13C10[3][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_0_s0/CLK
0.531 | 0.180 | tC2Q | RR | 1 | R13C10[3][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_ch_0_s0/Q
0.775 | 0.244 | tNET | RR | 1 | R14C9[1][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_Z_s/I0
1.033 | 0.257 | tINS | RF | 1 | R14C9[1][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_init_rmove_mod/sys_reset_Z_s/F
1.033 | 0.000 | tNET | FF | 1 | R14C9[1][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.043 | 0.361 | tNET | RR | 1 | R14C9[1][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0/CLK
1.078 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0
1.080 | 0.001 | tHld |  | 1 | R14C9[1][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_sync/recalib_s_0_s0

Path Statistics:

Clock Skew | 0.692
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.351, 100.000%
Arrival Data Path Delay | cell: 0.257, 37.798%; route: 0.244, 35.780%; tC2Q: 0.180, 26.422%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.361, 100.000%

### Path22

Path Summary:

Slack | 0.004
Data Arrival Time | 31.090
Data Required Time | 31.086
From | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_4_s0
To | RAW2RGB/r1_RAW_Data_s_4_s0
Launch Clk | RAW2RGB/clk_ce:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
30.000 | 30.000 |  |  |  |  | active clock edge time
30.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
30.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
30.356 | 0.356 | tNET | RR | 1 | R30C85[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_4_s0/CLK
30.536 | 0.180 | tC2Q | RR | 1 | R30C85[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_4_s0/Q
30.780 | 0.244 | tNET | RR | 1 | R34C85[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/Q_d_4_s/I1
31.090 | 0.310 | tINS | RF | 1 | R34C85[0][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/Q_d_4_s/F
31.090 | 0.000 | tNET | FF | 1 | R34C85[0][A] | RAW2RGB/r1_RAW_Data_s_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
30.000 | 30.000 |  |  |  |  | active clock edge time
30.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
30.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
31.050 | 0.368 | tNET | RR | 1 | R34C85[0][A] | RAW2RGB/r1_RAW_Data_s_4_s0/CLK
31.085 | 0.035 | tUnc |  |  |  | RAW2RGB/r1_RAW_Data_s_4_s0
31.086 | 0.001 | tHld |  | 1 | R34C85[0][A] | RAW2RGB/r1_RAW_Data_s_4_s0

Path Statistics:

Clock Skew | 0.694
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.356, 100.000%
Arrival Data Path Delay | cell: 0.310, 42.249%; route: 0.244, 33.220%; tC2Q: 0.180, 24.532%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%

### Path23

Path Summary:

Slack | 0.031
Data Arrival Time | 31.118
Data Required Time | 31.086
From | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_6_s0
To | RAW2RGB/r1_RAW_Data_s_6_s0
Launch Clk | RAW2RGB/clk_ce:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
30.000 | 30.000 |  |  |  |  | active clock edge time
30.000 | 0.000 |  |  |  |  | RAW2RGB/clk_ce
30.000 | 0.000 | tCL | RR | 8211 | TOPRIGHT | RAW2RGB/DCE/CLKOUT
30.392 | 0.392 | tNET | RR | 1 | R25C85[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_6_s0/CLK
30.573 | 0.180 | tC2Q | RR | 1 | R25C85[1][A] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/wdata_q_6_s0/Q
30.926 | 0.354 | tNET | RR | 1 | R34C85[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/Q_d_6_s/I1
31.118 | 0.191 | tINS | RF | 1 | R34C85[0][B] | RAW2RGB/c_shift_ram_0/u_RAM_based_shift_reg/Q_d_6_s/F
31.118 | 0.000 | tNET | FF | 1 | R34C85[0][B] | RAW2RGB/r1_RAW_Data_s_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
30.000 | 30.000 |  |  |  |  | active clock edge time
30.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT3.default_gen_clk
30.682 | 0.682 | tCL | RR | 130 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT3
31.050 | 0.368 | tNET | RR | 1 | R34C85[0][B] | RAW2RGB/r1_RAW_Data_s_6_s0/CLK
31.085 | 0.035 | tUnc |  |  |  | RAW2RGB/r1_RAW_Data_s_6_s0
31.086 | 0.001 | tHld |  | 1 | R34C85[0][B] | RAW2RGB/r1_RAW_Data_s_6_s0

Path Statistics:

Clock Skew | 0.657
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.392, 100.000%
Arrival Data Path Delay | cell: 0.191, 26.379%; route: 0.354, 48.793%; tC2Q: 0.180, 24.828%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%

### Path24

Path Summary:

Slack | 0.072
Data Arrival Time | 0.685
Data Required Time | 0.613
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.381 | 0.381 | tNET | RR | 1 | R8C27[2][B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/CLK
0.561 | 0.180 | tC2Q | RR | 1 | R8C27[2][B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_16_s0/Q
0.685 | 0.124 | tNET | RR | 1 | BSRAM_R10[7] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/DI[16]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.364 | 0.364 | tNET | RR | 1 | BSRAM_R10[7] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA
0.613 | 0.249 | tHld |  | 1 | BSRAM_R10[7] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Path Statistics:

Clock Skew | -0.018
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.381, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.124, 40.741%; tC2Q: 0.180, 59.259%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.364, 100.000%

### Path25

Path Summary:

Slack | 0.078
Data Arrival Time | 0.696
Data Required Time | 0.618
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s
Launch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.390 | 0.390 | tNET | RR | 1 | R6C17[2][B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0/CLK
0.570 | 0.180 | tC2Q | RR | 1 | R6C17[2][B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_dq_54_s0/Q
0.696 | 0.126 | tNET | RR | 1 | BSRAM_R10[4] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/DI[22]

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.369 | 0.369 | tNET | RR | 1 | BSRAM_R10[4] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKA
0.618 | 0.249 | tHld |  | 1 | BSRAM_R10[4] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_1_s

Path Statistics:

Clock Skew | -0.021
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.390, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.126, 41.224%; tC2Q: 0.180, 58.776%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.369, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -1.727
Data Arrival Time | 4.573
Data Required Time | 2.846
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 10 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
2.846 | -0.487 | tSu |  | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path2

Path Summary:

Slack | -1.727
Data Arrival Time | 4.573
Data Required Time | 2.846
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 10 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
2.846 | -0.487 | tSu |  | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path3

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
3.182 | -0.151 | tSu |  | 1 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path4

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
3.182 | -0.151 | tSu |  | 1 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path5

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
3.182 | -0.151 | tSu |  | 1 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path6

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
3.182 | -0.151 | tSu |  | 1 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path7

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
3.182 | -0.151 | tSu |  | 1 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path8

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
3.182 | -0.151 | tSu |  | 1 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path9

Path Summary:

Slack | -1.391
Data Arrival Time | 4.573
Data Required Time | 3.182
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT43[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
3.182 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
3.182 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.368 | 0.186 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
3.368 | 0.000 | tNET | FF | 1 | IOT43[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/FCLK
3.333 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen
3.182 | -0.151 | tSu |  | 1 | IOT43[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen

Path Statistics:

Clock Skew | -0.670
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.186, 100.000%; route: 0.000, 0.000%

### Path10

Path Summary:

Slack | 0.767
Data Arrival Time | 4.573
Data Required Time | 5.340
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 10 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.340 | -0.489 | tSu |  | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path11

Path Summary:

Slack | 0.767
Data Arrival Time | 4.573
Data Required Time | 5.340
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 10 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
5.340 | -0.489 | tSu |  | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path12

Path Summary:

Slack | 1.103
Data Arrival Time | 4.573
Data Required Time | 5.676
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
5.676 | -0.153 | tSu |  | 1 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path13

Path Summary:

Slack | 1.103
Data Arrival Time | 4.573
Data Required Time | 5.676
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
5.676 | -0.153 | tSu |  | 1 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path14

Path Summary:

Slack | 1.103
Data Arrival Time | 4.573
Data Required Time | 5.676
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
5.676 | -0.153 | tSu |  | 1 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path15

Path Summary:

Slack | 1.103
Data Arrival Time | 4.573
Data Required Time | 5.676
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
5.676 | -0.153 | tSu |  | 1 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path16

Path Summary:

Slack | 1.103
Data Arrival Time | 4.573
Data Required Time | 5.676
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
5.676 | -0.153 | tSu |  | 1 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path17

Path Summary:

Slack | 1.103
Data Arrival Time | 4.573
Data Required Time | 5.676
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
5.000 | 5.000 |  |  |  |  | active clock edge time
5.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
5.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
5.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
5.864 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
5.864 | 0.000 | tNET | RR | 1 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/FCLK
5.829 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
5.676 | -0.153 | tSu |  | 1 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew | -0.674
Setup Relationship | 5.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%

### Path18

Path Summary:

Slack | 15.790
Data Arrival Time | 4.573
Data Required Time | 20.363
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 10 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.896 | 0.896 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
20.861 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
20.363 | -0.498 | tSu |  | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew | -0.641
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.896, 100.000%

### Path19

Path Summary:

Slack | 15.809
Data Arrival Time | 4.573
Data Required Time | 20.382
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 10 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.915 | 0.915 | tNET | RR | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/PCLK
20.880 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs
20.382 | -0.498 | tSu |  | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs

Path Statistics:

Clock Skew | -0.623
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.915, 100.000%

### Path20

Path Summary:

Slack | 16.135
Data Arrival Time | 4.573
Data Required Time | 20.708
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.896 | 0.896 | tNET | RR | 1 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK
20.861 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen
20.708 | -0.153 | tSu |  | 1 | IOT50[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen

Path Statistics:

Clock Skew | -0.641
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.896, 100.000%

### Path21

Path Summary:

Slack | 16.135
Data Arrival Time | 4.573
Data Required Time | 20.708
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.896 | 0.896 | tNET | RR | 1 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK
20.861 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen
20.708 | -0.153 | tSu |  | 1 | IOT37[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen

Path Statistics:

Clock Skew | -0.641
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.896, 100.000%

### Path22

Path Summary:

Slack | 16.145
Data Arrival Time | 4.573
Data Required Time | 20.718
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.906 | 0.906 | tNET | RR | 1 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK
20.871 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen
20.718 | -0.153 | tSu |  | 1 | IOT33[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen

Path Statistics:

Clock Skew | -0.632
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.906, 100.000%

### Path23

Path Summary:

Slack | 16.145
Data Arrival Time | 4.573
Data Required Time | 20.718
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.906 | 0.906 | tNET | RR | 1 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK
20.871 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen
20.718 | -0.153 | tSu |  | 1 | IOT31[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen

Path Statistics:

Clock Skew | -0.632
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.906, 100.000%

### Path24

Path Summary:

Slack | 16.154
Data Arrival Time | 4.573
Data Required Time | 20.727
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.915 | 0.915 | tNET | RR | 1 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen/PCLK
20.880 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen
20.727 | -0.153 | tSu |  | 1 | IOT56[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/u_ck_gen

Path Statistics:

Clock Skew | -0.623
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.915, 100.000%

### Path25

Path Summary:

Slack | 16.154
Data Arrival Time | 4.573
Data Required Time | 20.727
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.538 | 0.856 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.905 | 0.368 | tC2Q | RF | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
4.573 | 2.668 | tNET | FF | 2 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.915 | 0.915 | tNET | RR | 1 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/PCLK
20.880 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen
20.727 | -0.153 | tSu |  | 1 | IOT39[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/u_ddr_phy_cmd_lane/u_ddr_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen

Path Statistics:

Clock Skew | -0.623
Setup Relationship | 20.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.856, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.668, 87.893%; tC2Q: 0.368, 12.107%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.915, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 1.135
Data Arrival Time | 2.530
Data Required Time | 1.394
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.206 | 0.368 | tINS | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.206 | 0.000 | tNET | RR | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.241 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.394 | 0.153 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.161
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.524, 100.000%; route: 0.000, 0.000%

### Path2

Path Summary:

Slack | 1.135
Data Arrival Time | 2.530
Data Required Time | 1.394
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.206 | 0.368 | tINS | RR | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.206 | 0.000 | tNET | RR | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.241 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.394 | 0.153 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.161
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.524, 100.000%; route: 0.000, 0.000%

### Path3

Path Summary:

Slack | 1.224
Data Arrival Time | 2.530
Data Required Time | 1.305
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.117 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.117 | 0.000 | tNET | RR | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
1.152 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.305 | 0.153 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | 0.072
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.435, 100.000%; route: 0.000, 0.000%

### Path4

Path Summary:

Slack | 1.224
Data Arrival Time | 2.530
Data Required Time | 1.305
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.117 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.117 | 0.000 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
1.152 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.305 | 0.153 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | 0.072
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.435, 100.000%; route: 0.000, 0.000%

### Path5

Path Summary:

Slack | 1.224
Data Arrival Time | 2.530
Data Required Time | 1.305
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.117 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.117 | 0.000 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
1.152 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.305 | 0.153 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | 0.072
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.435, 100.000%; route: 0.000, 0.000%

### Path6

Path Summary:

Slack | 1.224
Data Arrival Time | 2.530
Data Required Time | 1.305
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.117 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.117 | 0.000 | tNET | RR | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
1.152 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.305 | 0.153 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | 0.072
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.435, 100.000%; route: 0.000, 0.000%

### Path7

Path Summary:

Slack | 1.224
Data Arrival Time | 2.530
Data Required Time | 1.305
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT76[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.117 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.117 | 0.000 | tNET | RR | 1 | IOT76[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TCLK
1.152 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
1.305 | 0.153 | tHld |  | 1 | IOT76[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem

Path Statistics:

Clock Skew | 0.072
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.435, 100.000%; route: 0.000, 0.000%

### Path8

Path Summary:

Slack | 1.503
Data Arrival Time | 2.530
Data Required Time | 1.026
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
0.873 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.026 | 0.153 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | -0.207
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.156, 100.000%; route: 0.000, 0.000%

### Path9

Path Summary:

Slack | 1.503
Data Arrival Time | 2.530
Data Required Time | 1.026
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
0.873 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.026 | 0.153 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | -0.207
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.156, 100.000%; route: 0.000, 0.000%

### Path10

Path Summary:

Slack | 1.503
Data Arrival Time | 2.530
Data Required Time | 1.026
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK
0.873 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.026 | 0.153 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | -0.207
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.156, 100.000%; route: 0.000, 0.000%

### Path11

Path Summary:

Slack | 1.503
Data Arrival Time | 2.530
Data Required Time | 1.026
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK
0.873 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.026 | 0.153 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | -0.207
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.156, 100.000%; route: 0.000, 0.000%

### Path12

Path Summary:

Slack | 1.503
Data Arrival Time | 2.530
Data Required Time | 1.026
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK
0.873 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.026 | 0.153 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | -0.207
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.156, 100.000%; route: 0.000, 0.000%

### Path13

Path Summary:

Slack | 1.503
Data Arrival Time | 2.530
Data Required Time | 1.026
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
0.682 | 0.682 | tCL | RR | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
0.682 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.838 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.838 | 0.000 | tNET | RR | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK
0.873 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.026 | 0.153 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | -0.207
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.156, 100.000%; route: 0.000, 0.000%

### Path14

Path Summary:

Slack | 1.936
Data Arrival Time | 2.530
Data Required Time | 0.594
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406 | 0.406 | tNET | RR | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.441 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.594 | 0.153 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | -0.639
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.406, 100.000%

### Path15

Path Summary:

Slack | 1.936
Data Arrival Time | 2.530
Data Required Time | 0.594
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406 | 0.406 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK
0.441 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
0.594 | 0.153 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | -0.639
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.406, 100.000%

### Path16

Path Summary:

Slack | 1.936
Data Arrival Time | 2.530
Data Required Time | 0.594
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.406 | 0.406 | tNET | RR | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/PCLK
0.441 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
0.594 | 0.153 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | -0.639
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.406, 100.000%

### Path17

Path Summary:

Slack | 1.941
Data Arrival Time | 2.530
Data Required Time | 0.589
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.401 | 0.401 | tNET | RR | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.436 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.589 | 0.153 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | -0.644
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.401, 100.000%

### Path18

Path Summary:

Slack | 1.941
Data Arrival Time | 2.530
Data Required Time | 0.589
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.401 | 0.401 | tNET | RR | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
0.436 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
0.589 | 0.153 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | -0.644
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.401, 100.000%

### Path19

Path Summary:

Slack | 1.941
Data Arrival Time | 2.530
Data Required Time | 0.589
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 3257 | TOPSIDE[0] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.401 | 0.401 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.436 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
0.589 | 0.153 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | -0.644
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.401, 100.000%

### Path20

Path Summary:

Slack | 3.610
Data Arrival Time | 2.530
Data Required Time | -1.081
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
-1.818 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
-1.818 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.656 | 0.000 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.267 | 0.389 | tINS | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-1.267 | 0.000 | tNET | FF | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-1.232 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-1.081 | 0.151 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.188
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.551, 100.000%; route: 0.000, 0.000%

### Path21

Path Summary:

Slack | 3.610
Data Arrival Time | 2.530
Data Required Time | -1.081
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
-1.818 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
-1.818 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.656 | 0.000 | tNET | FF | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.267 | 0.389 | tINS | FF | 1 | R0C60 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-1.267 | 0.000 | tNET | FF | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-1.232 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-1.081 | 0.151 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.188
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.551, 100.000%; route: 0.000, 0.000%

### Path22

Path Summary:

Slack | 3.711
Data Arrival Time | 2.530
Data Required Time | -1.181
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
-1.818 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
-1.818 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.656 | 0.000 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.367 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.367 | 0.000 | tNET | FF | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
-1.332 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
-1.181 | 0.151 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | 0.088
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.451, 100.000%; route: 0.000, 0.000%

### Path23

Path Summary:

Slack | 3.711
Data Arrival Time | 2.530
Data Required Time | -1.181
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
-1.818 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
-1.818 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.656 | 0.000 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.367 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.367 | 0.000 | tNET | FF | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
-1.332 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
-1.181 | 0.151 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | 0.088
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.451, 100.000%; route: 0.000, 0.000%

### Path24

Path Summary:

Slack | 3.711
Data Arrival Time | 2.530
Data Required Time | -1.181
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
-1.818 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
-1.818 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.656 | 0.000 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.367 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.367 | 0.000 | tNET | FF | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
-1.332 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
-1.181 | 0.151 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | 0.088
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.451, 100.000%; route: 0.000, 0.000%

### Path25

Path Summary:

Slack | 3.711
Data Arrival Time | 2.530
Data Required Time | -1.181
From | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT0.default_gen_clk
0.682 | 0.682 | tCL | RR | 141 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT0
1.045 | 0.363 | tNET | RR | 1 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.225 | 0.180 | tC2Q | RR | 2196 | R34C4[0][A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.530 | 1.305 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | Gowin_PLL/PLLA_inst/CLKOUT2.default_gen_clk
-1.818 | 0.682 | tCL | FF | 1 | PLL_B | Gowin_PLL/PLLA_inst/CLKOUT2
-1.818 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.656 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.656 | 0.000 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.367 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.367 | 0.000 | tNET | FF | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
-1.332 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
-1.181 | 0.151 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/DDR3_Memory_Interface_Top/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | 0.088
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.305, 87.876%; tC2Q: 0.180, 12.124%
Required Clock Path Delay | cell: 0.451, 100.000%; route: 0.000, 0.000%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 3.146
Actual Width: | 4.146
Required Width: | 1.000
Type: | High Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
0.683 | 0.683 | tINS | RR | camera_pclk_ibuf/O
2.326 | 1.643 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.677 | 0.678 | tINS | FF | camera_pclk_ibuf/O
6.472 | 0.795 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

### MPW2

MPW Summary:

Slack: | 3.151
Actual Width: | 4.151
Required Width: | 1.000
Type: | High Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
0.683 | 0.683 | tINS | RR | camera_pclk_ibuf/O
2.317 | 1.634 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.677 | 0.678 | tINS | FF | camera_pclk_ibuf/O
6.467 | 0.790 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

### MPW3

MPW Summary:

Slack: | 3.151
Actual Width: | 4.151
Required Width: | 1.000
Type: | High Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
0.683 | 0.683 | tINS | RR | camera_pclk_ibuf/O
2.317 | 1.634 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.677 | 0.678 | tINS | FF | camera_pclk_ibuf/O
6.467 | 0.790 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

### MPW4

MPW Summary:

Slack: | 3.155
Actual Width: | 4.155
Required Width: | 1.000
Type: | High Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
0.683 | 0.683 | tINS | RR | camera_pclk_ibuf/O
2.307 | 1.625 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.677 | 0.678 | tINS | FF | camera_pclk_ibuf/O
6.462 | 0.785 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

### MPW5

MPW Summary:

Slack: | 3.177
Actual Width: | 4.177
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.688 | 0.688 | tINS | FF | camera_pclk_ibuf/O
7.302 | 1.615 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | camera_pclk
10.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
10.675 | 0.675 | tINS | RR | camera_pclk_ibuf/O
11.479 | 0.804 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_1_s/CLKA

### MPW6

MPW Summary:

Slack: | 3.181
Actual Width: | 4.181
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.688 | 0.688 | tINS | FF | camera_pclk_ibuf/O
7.293 | 1.605 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | camera_pclk
10.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
10.675 | 0.675 | tINS | RR | camera_pclk_ibuf/O
11.474 | 0.799 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_2_s/CLKA

### MPW7

MPW Summary:

Slack: | 3.181
Actual Width: | 4.181
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.688 | 0.688 | tINS | FF | camera_pclk_ibuf/O
7.293 | 1.605 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | camera_pclk
10.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
10.675 | 0.675 | tINS | RR | camera_pclk_ibuf/O
11.474 | 0.799 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

### MPW8

MPW Summary:

Slack: | 3.186
Actual Width: | 4.186
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | camera_pclk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.688 | 0.688 | tINS | FF | camera_pclk_ibuf/O
7.283 | 1.596 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | camera_pclk
10.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
10.675 | 0.675 | tINS | RR | camera_pclk_ibuf/O
11.469 | 0.794 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_3_s/CLKA

### MPW9

MPW Summary:

Slack: | 3.887
Actual Width: | 4.137
Required Width: | 0.250
Type: | High Pulse Width
Clock: | camera_pclk
Objects: | DVP_Capture/r_Data_6_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
0.683 | 0.683 | tINS | RR | camera_pclk_ibuf/O
2.369 | 1.687 | tNET | RR | DVP_Capture/r_Data_6_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.677 | 0.678 | tINS | FF | camera_pclk_ibuf/O
6.507 | 0.829 | tNET | FF | DVP_Capture/r_Data_6_s0/CLK

### MPW10

MPW Summary:

Slack: | 3.887
Actual Width: | 4.137
Required Width: | 0.250
Type: | High Pulse Width
Clock: | camera_pclk
Objects: | DVP_Capture/r_Data_7_s0

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
0.000 | 0.000 |  |  | active clock edge time
0.000 | 0.000 |  |  | camera_pclk
0.000 | 0.000 | tCL | RR | camera_pclk_ibuf/I
0.683 | 0.683 | tINS | RR | camera_pclk_ibuf/O
2.367 | 1.684 | tNET | RR | DVP_Capture/r_Data_7_s0/CLK

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
5.000 | 0.000 |  |  | active clock edge time
5.000 | 0.000 |  |  | camera_pclk
5.000 | 0.000 | tCL | FF | camera_pclk_ibuf/I
5.677 | 0.678 | tINS | FF | camera_pclk_ibuf/O
6.504 | 0.827 | tNET | FF | DVP_Capture/r_Data_7_s0/CLK

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
8211 | clk_ce | -3.114 | 0.922
4114 | wbin[9] | -3.034 | 6.678
3257 | ui_clk | -3.602 | 0.934
2196 | ui_clk_sync_rst | -1.727 | 2.711
2067 | wbin[8] | -3.072 | 7.875
1045 | wbin[2] | -3.009 | 6.299
1043 | wbin[7] | -3.114 | 8.226
1030 | wbin[1] | -2.438 | 6.831
1024 | n170_6 | -13.451 | 7.464
1024 | n171_6 | -13.024 | 7.246

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R15C57 | 73.61%
R11C42 | 70.83%
R10C12 | 69.44%
R10C26 | 69.44%
R20C73 | 69.44%
R18C69 | 69.44%
R22C50 | 68.06%
R18C58 | 68.06%
R10C17 | 66.67%
R18C71 | 66.67%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---