- Synthesis Messages
- Synthesis Details
- Resource
  - Resource Usage Summary
  - Resource Utilization Summary
- Timing
  - Clock Summary
  - Max Frequency Summary
  - Detail Timing Paths Informations

# Synthesis Messages

Report Title | GowinSynthesis Report
Design File | H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\bit8_trans_bit16\bit8_trans_bit16.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\ddr3_ctrl_2port\ddr3_ctrl_2port.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\ddr3_ctrl_2port\fifo_ddr3_adapter.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\ddr3_memory_interface\ddr3_memory_interface.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\ddr3_pll\ddr3_pll.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\disp_driver\disp_driver.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\disp_driver\disp_parameter_cfg.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\dvi_encoder.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\gowin_ddr\gowin_ddr.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\gowin_prom\rom_red_x77.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\image_buffer\image_buffer.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\image_rx_ctrl\image_rx_ctrl.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\image_stitche\image_stitche_x.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\pll\pll.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\rd_data_fifo\rd_data_fifo.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\rgb2gray\rgb2gray.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\rom_blue_x29\rom_blue_x29.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\rom_green_x150\rom_green_x150.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\shift_reg.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\shift_reg_ram\shift_reg_ram.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\test_dat_gen\colour_bar_dat_gen.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\test_dat_gen\rom_image.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\test_dat_gen\rom_image_extract.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\test_dat_gen\test_dat_gen.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\uart_byte_rx\uart_byte_rx.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\uart_ddr3_tft_hdmi_sobel_filter.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\wr_data_fifo\wr_data_fifo.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\sobel\sobel.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\sobel\shift_register_2taps\shift_register_2taps.v H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\key_filter.v
GowinSynthesis Constraints File | ---
Version | V1.9.9 Beta-3
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Wed Aug 30 14:37:37 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

# Synthesis Details

Top Level Module | uart_ddr3_tft_hdmi_sobel_filter
Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 526.910MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.546s, Peak memory usage = 526.910MB Optimizing Phase 1: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.538s, Peak memory usage = 526.910MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 526.910MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.274s, Peak memory usage = 526.910MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 526.910MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 526.910MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 526.910MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 526.910MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 526.910MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 526.910MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 526.910MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.626s, Peak memory usage = 526.910MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 526.910MB
Total Time and Memory Usage | CPU time = 0h 0m 11s, Elapsed time = 0h 0m 12s, Peak memory usage = 526.910MB

# Resource

## Resource Usage Summary

Resource | Usage
I/O Port | 95
I/O Buf | 92
IBUF | 4
OBUF | 67
TBUF | 2
IOBUF | 16
ELVDS_OBUF | 1
ELVDS_IOBUF | 2
Register | 12077
DFFSE | 3
DFFRE | 8954
DFFPE | 87
DFFCE | 3033
LUT | 9434
LUT2 | 650
LUT3 | 5988
LUT4 | 2796
ALU | 519
ALU | 519
SSRAM | 12
RAM16S4 | 12
INV | 57
INV | 57
IOLOGIC | 84
ODDR | 8
IDES8_MEM | 16
OSER8 | 24
OSER8_MEM | 20
IODELAY | 16
BSRAM | 22
SDPB | 14
SDPX9B | 8
CLOCK | 9
CLKDIV | 2
DQS | 2
DCE | 1
DDRDLL | 1
DHCE | 1
PLLA | 2

## Resource Utilization Summary

Resource | Usage | Utilization
Logic | 10082(9491 LUT, 519 ALU, 12 RAM16) / 23040 | 44%
Register | 12077 / 23685 | 51%
--Register as Latch | 0 / 23685 | 0%
--Register as FF | 12077 / 23685 | 51%
BSRAM | 22 / 56 | 40%

# Timing

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk50m | Base | 20.000 | 50.0 | 0.000 | 10.000 |  |  | clk50m_ibuf/I
sobel/shift_register_2taps/clk_ce | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | sobel/shift_register_2taps/DCE/CLKOUT
image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/n4_s2/O
image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/n9_s2/O
image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/n4_s2/O
image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/n9_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_s2/O
ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_s2/O
ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/n1784_s2/O
ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk50m_ibuf/I | clk50m | ddr3_pll/PLLA_inst/CLKOUT0
ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 5.000 | 200.0 | 0.000 | 2.500 | clk50m_ibuf/I | clk50m | ddr3_pll/PLLA_inst/CLKOUT1
pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 6.061 | 165.0 | 0.000 | 3.030 | ddr3_pll/PLLA_inst/CLKOUT0 | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | pll/PLLA_inst/CLKOUT0
u_clkdiv/CLKOUT.default_gen_clk | Generated | 30.303 | 33.0 | 0.000 | 15.152 | pll/PLLA_inst/CLKOUT0 | pll/PLLA_inst/CLKOUT0.default_gen_clk | u_clkdiv/CLKOUT
ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | ddr3_pll/PLLA_inst/CLKOUT1 | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

## Max Frequency Summary:

No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | sobel/shift_register_2taps/clk_ce | 100.0(MHz) | 255.5(MHz) | 4 | TOP
2 | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
3 | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
4 | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
5 | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
6 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
7 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
8 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n4_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
9 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/n9_6 | 100.0(MHz) | 1643.7(MHz) | 1 | TOP
10 | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | 50.0(MHz) | 123.8(MHz) | 6 | TOP
11 | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | 200.0(MHz) | 1506.0(MHz) | 1 | TOP
12 | pll/PLLA_inst/CLKOUT0.default_gen_clk | 165.0(MHz) | 521.8(MHz) | 3 | TOP
13 | u_clkdiv/CLKOUT.default_gen_clk | 33.0(MHz) | 123.4(MHz) | 6 | TOP
14 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 103.2(MHz) | 8 | TOP

## Detail Timing Paths Information

### Path 1

Path Summary:

Slack | -0.038
Data Arrival Time | 940.273
Data Required Time | 940.236
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_0_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_0_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
939.394 | 0.000 |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
939.546 | 0.152 | tCL | RR | 189 | u_clkdiv/CLKOUT
939.726 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_0_s0/CLK
940.094 | 0.367 | tC2Q | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_0_s0/Q
940.273 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
940.000 | 0.000 |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
940.152 | 0.152 | tCL | RR | 3222 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
940.332 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_0_s0/CLK
940.297 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_0_s0
940.236 | -0.061 | tSu |  | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_0_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 0.606
Logic Level: | 1
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.180, 32.895%; tC2Q: 0.367, 67.105%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%

### Path 2

Path Summary:

Slack | -0.038
Data Arrival Time | 940.273
Data Required Time | 940.236
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_1_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_1_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
939.394 | 0.000 |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
939.546 | 0.152 | tCL | RR | 189 | u_clkdiv/CLKOUT
939.726 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_1_s0/CLK
940.094 | 0.367 | tC2Q | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_1_s0/Q
940.273 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
940.000 | 0.000 |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
940.152 | 0.152 | tCL | RR | 3222 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
940.332 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_1_s0/CLK
940.297 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_1_s0
940.236 | -0.061 | tSu |  | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_1_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 0.606
Logic Level: | 1
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.180, 32.895%; tC2Q: 0.367, 67.105%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%

### Path 3

Path Summary:

Slack | -0.038
Data Arrival Time | 940.273
Data Required Time | 940.236
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_2_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_2_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
939.394 | 0.000 |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
939.546 | 0.152 | tCL | RR | 189 | u_clkdiv/CLKOUT
939.726 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_2_s0/CLK
940.094 | 0.367 | tC2Q | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_2_s0/Q
940.273 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
940.000 | 0.000 |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
940.152 | 0.152 | tCL | RR | 3222 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
940.332 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_2_s0/CLK
940.297 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_2_s0
940.236 | -0.061 | tSu |  | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_2_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 0.606
Logic Level: | 1
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.180, 32.895%; tC2Q: 0.367, 67.105%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%

### Path 4

Path Summary:

Slack | -0.038
Data Arrival Time | 940.273
Data Required Time | 940.236
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_3_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_3_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
939.394 | 0.000 |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
939.546 | 0.152 | tCL | RR | 189 | u_clkdiv/CLKOUT
939.726 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_3_s0/CLK
940.094 | 0.367 | tC2Q | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_3_s0/Q
940.273 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
940.000 | 0.000 |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
940.152 | 0.152 | tCL | RR | 3222 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
940.332 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_3_s0/CLK
940.297 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_3_s0
940.236 | -0.061 | tSu |  | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_3_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 0.606
Logic Level: | 1
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.180, 32.895%; tC2Q: 0.367, 67.105%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%

### Path 5

Path Summary:

Slack | -0.038
Data Arrival Time | 940.273
Data Required Time | 940.236
From | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_4_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
939.394 | 0.000 |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
939.546 | 0.152 | tCL | RR | 189 | u_clkdiv/CLKOUT
939.726 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_4_s0/CLK
940.094 | 0.367 | tC2Q | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.rptr_4_s0/Q
940.273 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | NODE
--- | --- | --- | --- | --- | ---
940.000 | 0.000 |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
940.152 | 0.152 | tCL | RR | 3222 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
940.332 | 0.180 | tNET | RR | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_4_s0/CLK
940.297 | -0.035 | tUnc |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_4_s0
940.236 | -0.061 | tSu |  | 1 | ddr3_ctrl_2port/fifo_ddr3_adapter/rd_data_fifo/fifo_inst/Small.wq1_rptr_4_s0

Path Statistics:

Clock Skew: | 0.000
Setup Relationship: | 0.606
Logic Level: | 1
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.180, 32.895%; tC2Q: 0.367, 67.105%
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000%