# Timing Messages

Report Title | Timing Analysis Report
Design File | H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\impl\gwsynthesis\uart_ddr3_tft_hdmi_sobel_filter.vg
Physical Constraints File | H:\01_gaoyun\gao_project\60_uart_ddr3_tft_hdmi_sobel_filter\uart_ddr3_tft_hdmi_sobel_filter\src\uart_ddr3_tft_hdmi_sobel_filter.cst
Timing Constraint File | ---
Version | V1.9.9 Beta-3
Part Number | GW5A-LV25UG324ES
Device | GW5A-25
Device Version | A
Created Time | Wed Aug 30 14:39:15 2023
Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

# Timing Summaries

## STA Tool Run Summary:

Setup Delay Model | Slow 0.85V -40C ES
Hold Delay Model | Fast 0.95V 100C ES
Numbers of Paths Analyzed | 57051
Numbers of Endpoints Analyzed | 26373
Numbers of Falling Endpoints | 68
Numbers of Setup Violated Endpoints | 1477
Numbers of Hold Violated Endpoints | 29

## Clock Summary:

Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects
--- | --- | --- | --- | --- | --- | --- | --- | ---
clk50m | Base | 20.000 | 50.000 | 0.000 | 10.000 |  |  | clk50m_ibuf/I
sobel/shift_register_2taps/clk_ce | Base | 10.000 | 100.000 | 0.000 | 5.000 |  |  | sobel/shift_register_2taps/DCE/CLKOUT
ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | clk50m_ibuf/I | clk50m | ddr3_pll/PLLA_inst/CLKOUT0
ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk50m_ibuf/I | clk50m | ddr3_pll/PLLA_inst/CLKOUT1
pll/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 6.061 | 165.000 | 0.000 | 3.030 | ddr3_pll/PLLA_inst/CLKOUT0 | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | pll/PLLA_inst/CLKOUT0
u_clkdiv/CLKOUT.default_gen_clk | Generated | 30.303 | 33.000 | 0.000 | 15.152 | pll/PLLA_inst/CLKOUT0 | pll/PLLA_inst/CLKOUT0.default_gen_clk | u_clkdiv/CLKOUT
ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | ddr3_pll/PLLA_inst/CLKOUT1 | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT

## Max Frequency Summary:

NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity
--- | --- | --- | --- | --- | ---
1 | sobel/shift_register_2taps/clk_ce | 100.000(MHz) | 93.551(MHz) | 4 | TOP
2 | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 103.681(MHz) | 12 | TOP
3 | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | 200.000(MHz) | 2016.130(MHz) | 1 | TOP
4 | pll/PLLA_inst/CLKOUT0.default_gen_clk | 165.000(MHz) | 203.973(MHz) | 2 | TOP
5 | u_clkdiv/CLKOUT.default_gen_clk | 33.000(MHz) | 93.630(MHz) | 5 | TOP
6 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.000(MHz) | 79.431(MHz) | 10 | TOP

#### No timing paths to get frequency of clk50m!

## Total Negative Slack Summary:

Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints
--- | --- | --- | ---
clk50m | Setup | 0.000 | 0
clk50m | Hold | 0.000 | 0
sobel/shift_register_2taps/clk_ce | Setup | -50.148 | 202
sobel/shift_register_2taps/clk_ce | Hold | 0.000 | 0
ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0
ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0
ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | Setup | 0.000 | 0
ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk | Hold | 0.000 | 0
pll/PLLA_inst/CLKOUT0.default_gen_clk | Setup | 0.000 | 0
pll/PLLA_inst/CLKOUT0.default_gen_clk | Hold | 0.000 | 0
u_clkdiv/CLKOUT.default_gen_clk | Setup | 0.000 | 0
u_clkdiv/CLKOUT.default_gen_clk | Hold | 0.000 | 0
ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Setup | 0.000 | 0
ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Hold | 0.000 | 0

# Timing Details

## Path Slacks Table:

### Setup Paths Table

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -4.740 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.398 | 9.245
2 | -4.363 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.386 | 8.880
3 | -4.233 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.384 | 8.752
4 | -4.226 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.377 | 8.752
5 | -4.220 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.393 | 8.736
6 | -4.220 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.393 | 8.736
7 | -4.152 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.386 | 8.669
8 | -3.951 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.380 | 8.475
9 | -3.944 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.377 | 8.252
10 | -3.475 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.380 | 8.000
11 | -2.587 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.375 | 7.116
12 | -2.180 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CEN | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | 2.500 | 0.373 | 4.091
13 | -1.948 | rgb2gray/PROC_FORMULA.sum_10_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_324_G[2]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.684 | 11.173
14 | -1.897 | rgb2gray/PROC_FORMULA.sum_11_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_429_G[3]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.681 | 10.902
15 | -1.895 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.372 | 6.426
16 | -1.886 | rgb2gray/PROC_FORMULA.sum_14_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_311_G[6]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.683 | 11.113
17 | -1.865 | rgb2gray/PROC_FORMULA.sum_14_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_302_G[6]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.651 | 11.124
18 | -1.822 | rgb2gray/PROC_FORMULA.sum_10_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_443_G[2]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.693 | 11.039
19 | -1.821 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_167_G[6]_s0/D | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.184 | 11.540
20 | -1.821 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_71_G[6]_s0/D | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.184 | 11.540
21 | -1.817 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_6_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.375 | 6.346
22 | -1.780 | rgb2gray/PROC_FORMULA.sum_14_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_263_G[6]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.681 | 11.009
23 | -1.770 | rgb2gray/PROC_FORMULA.sum_10_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_281_G[2]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.684 | 10.996
24 | -1.721 | rgb2gray/PROC_FORMULA.sum_11_s0/Q | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_471_G[3]_s0/D | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | sobel/shift_register_2taps/clk_ce:[R] | 10.000 | 0.681 | 10.950
25 | -1.720 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/D | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 5.000 | 0.372 | 6.251

### Hold Paths Table

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -0.311 | u_dvi_encoder/encr/dout_6_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.539
2 | -0.266 | u_dvi_encoder/encb/dout_9_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.819 | 0.407
3 | -0.256 | u_dvi_encoder/encr/dout_8_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.803 | 0.401
4 | -0.253 | u_dvi_encoder/encr/dout_3_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.598
5 | -0.252 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/CALIB | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.601 | 0.384
6 | -0.243 | u_dvi_encoder/encg/dout_8_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.808 | 0.419
7 | -0.201 | u_dvi_encoder/encr/dout_4_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.819 | 0.654
8 | -0.148 | u_dvi_encoder/encr/dout_9_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.812 | 0.518
9 | -0.147 | u_dvi_encoder/encg/dout_9_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.808 | 0.515
10 | -0.142 | u_dvi_encoder/encr/dout_7_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.819 | 0.713
11 | -0.128 | u_dvi_encoder/encg/dout_6_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.809 | 0.718
12 | -0.125 | u_dvi_encoder/encb/dout_5_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.725
13 | -0.122 | u_dvi_encoder/encg/dout_2_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.809 | 0.724
14 | -0.119 | u_dvi_encoder/encr/dout_9_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.817 | 0.734
15 | -0.117 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/CALIB | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.601 | 0.520
16 | -0.080 | u_dvi_encoder/encg/dout_1_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.819 | 0.775
17 | -0.080 | u_dvi_encoder/encb/dout_3_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.770
18 | -0.080 | u_dvi_encoder/encb/dout_6_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.770
19 | -0.075 | u_dvi_encoder/encb/dout_8_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.593
20 | -0.058 | u_dvi_encoder/encg/dout_3_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.809 | 0.787
21 | -0.052 | u_dvi_encoder/encr/dout_5_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.819 | 0.803
22 | -0.045 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/CALIB | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.599 | 0.589
23 | -0.016 | u_dvi_encoder/encb/dout_4_s0/Q | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/D | u_clkdiv/CLKOUT.default_gen_clk:[R] | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.814 | 0.834
24 | -0.015 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/D | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.562 | 0.401
25 | -0.015 | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/Q | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/D | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | 0.000 | -0.562 | 0.401

### Recovery Paths Table

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | -2.528 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_6_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.182 | 2.584
2 | -2.528 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_7_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.182 | 2.584
3 | -2.528 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_8_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.182 | 2.584
4 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encb/cnt_1_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.171 | 2.591
5 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encb/cnt_3_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.171 | 2.591
6 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encr/dout_4_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.176 | 2.585
7 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encr/dout_5_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.176 | 2.585
8 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encr/dout_7_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.176 | 2.585
9 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encg/cnt_3_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.174 | 2.587
10 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encg/cnt_4_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.176 | 2.585
11 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encg/dout_1_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.176 | 2.585
12 | -2.524 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encb/cnt_2_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.172 | 2.589
13 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | u_dvi_encoder/encb/dout_9_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
14 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/vcount_r_0_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
15 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/vcount_r_1_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
16 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/vcount_r_2_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
17 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/vcount_r_3_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
18 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/vcount_r_4_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
19 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/vcount_r_8_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
20 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_0_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
21 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_1_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
22 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_2_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
23 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_3_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
24 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_4_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584
25 | -2.519 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q | disp_driver/hcount_r_5_s0/CLEAR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | 0.606 | 0.173 | 2.584

### Removal Paths Table

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay
--- | --- | --- | --- | --- | --- | --- | --- | ---
1 | 0.589 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.439 | 1.215
2 | 0.589 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.439 | 1.215
3 | 0.678 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.350 | 1.215
4 | 0.678 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.350 | 1.215
5 | 0.678 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.350 | 1.215
6 | 0.678 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.350 | 1.215
7 | 0.678 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.350 | 1.215
8 | 0.957 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.071 | 1.215
9 | 0.957 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.071 | 1.215
10 | 0.957 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.071 | 1.215
11 | 0.957 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.071 | 1.215
12 | 0.957 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.071 | 1.215
13 | 0.957 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R] | 0.000 | -0.071 | 1.215
14 | 1.671 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.643 | 1.215
15 | 1.675 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.648 | 1.215
16 | 1.675 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.648 | 1.215
17 | 1.675 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.648 | 1.215
18 | 1.680 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.653 | 1.215
19 | 1.680 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.000 | 0.653 | 1.215
20 | 3.064 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | -2.500 | -0.466 | 1.215
21 | 3.064 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | -2.500 | -0.466 | 1.215
22 | 3.164 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | -2.500 | -0.366 | 1.215
23 | 3.164 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | -2.500 | -0.366 | 1.215
24 | 3.164 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | -2.500 | -0.366 | 1.215
25 | 3.164 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R] | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F] | -2.500 | -0.366 | 1.215

## Minimum Pulse Width Table:

Number | Slack | Actual Width | Required Width | Type | Clock | Objects
--- | --- | --- | --- | --- | --- | ---

#### Report Command:report_min_pulse_width -nworst 10 -detail

1 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s
2 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s
3 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s
4 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s
5 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s
6 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
7 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s
8 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s
9 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s
10 | 8.826 | 9.826 | 1.000 | Low Pulse Width | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

## Timing Report By Analysis Type:

### Setup Analysis Report

#### Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -4.740
Data Arrival Time | 25.110
Data Required Time | 20.370
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.763 | 0.254 | tINS | RR | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.614 | 0.851 | tNET | RR | 1 | R11C79[0][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/I2
25.110 | 0.496 | tINS | RR | 1 | R11C79[0][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n215_s0/F
25.110 | 0.000 | tNET | RR | 1 | R11C79[0][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.466 | 0.342 | tNET | RR | 1 | R11C79[0][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0/CLK
20.431 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0
20.370 | -0.061 | tSu |  | 1 | R11C79[0][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_5_s0

Path Statistics:

Clock Skew | -0.398
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.821, 19.695%; route: 7.043, 76.178%; tC2Q: 0.382, 4.128%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.342, 100.000%

### Path2

Path Summary:

Slack | -4.363
Data Arrival Time | 24.745
Data Required Time | 20.382
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.763 | 0.254 | tINS | RR | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.245 | 0.481 | tNET | RR | 1 | R8C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s0/I2
24.745 | 0.500 | tINS | RR | 1 | R8C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n214_s0/F
24.745 | 0.000 | tNET | RR | 1 | R8C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.478 | 0.354 | tNET | RR | 1 | R8C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0/CLK
20.443 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0
20.382 | -0.061 | tSu |  | 1 | R8C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_6_s0

Path Statistics:

Clock Skew | -0.386
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.826, 20.558%; route: 6.673, 75.145%; tC2Q: 0.382, 4.297%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.354, 100.000%

### Path3

Path Summary:

Slack | -4.233
Data Arrival Time | 24.617
Data Required Time | 20.384
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.116 | 0.329 | tNET | FF | 1 | R9C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/I2
24.617 | 0.500 | tINS | FR | 1 | R9C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n216_s0/F
24.617 | 0.000 | tNET | RR | 1 | R9C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.480 | 0.356 | tNET | RR | 1 | R9C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0/CLK
20.445 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0
20.384 | -0.061 | tSu |  | 1 | R9C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_4_s0

Path Statistics:

Clock Skew | -0.384
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.850, 21.133%; route: 6.521, 74.506%; tC2Q: 0.382, 4.360%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.356, 100.000%

### Path4

Path Summary:

Slack | -4.226
Data Arrival Time | 24.617
Data Required Time | 20.391
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.116 | 0.329 | tNET | FF | 1 | R8C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/I2
24.617 | 0.500 | tINS | FR | 1 | R8C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n220_s0/F
24.617 | 0.000 | tNET | RR | 1 | R8C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.487 | 0.363 | tNET | RR | 1 | R8C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0/CLK
20.452 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0
20.391 | -0.061 | tSu |  | 1 | R8C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_0_s0

Path Statistics:

Clock Skew | -0.377
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.850, 21.133%; route: 6.521, 74.506%; tC2Q: 0.382, 4.360%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%

### Path5

Path Summary:

Slack | -4.220
Data Arrival Time | 24.601
Data Required Time | 20.381
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.323 | 0.535 | tNET | FF | 1 | R9C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/I2
24.601 | 0.278 | tINS | FF | 1 | R9C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n218_s0/F
24.601 | 0.000 | tNET | FF | 1 | R9C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.471 | 0.347 | tNET | RR | 1 | R9C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0/CLK
20.436 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0
20.381 | -0.055 | tSu |  | 1 | R9C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_2_s0

Path Statistics:

Clock Skew | -0.393
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.628, 18.630%; route: 6.727, 77.002%; tC2Q: 0.382, 4.368%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.347, 100.000%

### Path6

Path Summary:

Slack | -4.220
Data Arrival Time | 24.601
Data Required Time | 20.381
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.323 | 0.535 | tNET | FF | 1 | R9C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/I2
24.601 | 0.278 | tINS | FF | 1 | R9C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n217_s0/F
24.601 | 0.000 | tNET | FF | 1 | R9C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.471 | 0.347 | tNET | RR | 1 | R9C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0/CLK
20.436 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0
20.381 | -0.055 | tSu |  | 1 | R9C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_3_s0

Path Statistics:

Clock Skew | -0.393
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.628, 18.630%; route: 6.727, 77.002%; tC2Q: 0.382, 4.368%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.347, 100.000%

### Path7

Path Summary:

Slack | -4.152
Data Arrival Time | 24.534
Data Required Time | 20.382
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.135 | 0.348 | tNET | FF | 1 | R8C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/I2
24.534 | 0.398 | tINS | FR | 1 | R8C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n213_s0/F
24.534 | 0.000 | tNET | RR | 1 | R8C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.478 | 0.354 | tNET | RR | 1 | R8C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0/CLK
20.443 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0
20.382 | -0.061 | tSu |  | 1 | R8C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_7_s0

Path Statistics:

Clock Skew | -0.386
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.748, 20.159%; route: 6.540, 75.439%; tC2Q: 0.382, 4.402%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.354, 100.000%

### Path8

Path Summary:

Slack | -3.951
Data Arrival Time | 24.339
Data Required Time | 20.389
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
23.941 | 0.154 | tNET | FF | 1 | R7C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/I2
24.339 | 0.398 | tINS | FR | 1 | R7C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n219_s0/F
24.339 | 0.000 | tNET | RR | 1 | R7C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.485 | 0.361 | tNET | RR | 1 | R7C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0/CLK
20.450 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0
20.389 | -0.061 | tSu |  | 1 | R7C80[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/diff_dllstep_1_s0

Path Statistics:

Clock Skew | -0.380
Setup Relationship | 5.000
Logic Level | 6
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.748, 20.621%; route: 6.346, 74.876%; tC2Q: 0.382, 4.503%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.361, 100.000%

### Path9

Path Summary:

Slack | -3.944
Data Arrival Time | 24.116
Data Required Time | 20.173
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RR | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.509 | 0.391 | tNET | RR | 1 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/I1
23.787 | 0.278 | tINS | RF | 9 | R7C79[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n250_s1/F
24.116 | 0.329 | tNET | FF | 1 | R8C79[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.487 | 0.363 | tNET | RR | 1 | R8C79[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0/CLK
20.452 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0
20.173 | -0.280 | tSu |  | 1 | R8C79[3][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_0_s0

Path Statistics:

Clock Skew | -0.377
Setup Relationship | 5.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.349, 16.351%; route: 6.521, 79.025%; tC2Q: 0.382, 4.625%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.363, 100.000%

### Path10

Path Summary:

Slack | -3.475
Data Arrival Time | 23.864
Data Required Time | 20.389
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.453 | 5.801 | tNET | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/I1
22.926 | 0.473 | tINS | RR | 1 | R7C79[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s18/COUT
22.926 | 0.000 | tNET | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/CIN
22.974 | 0.048 | tINS | RR | 1 | R7C79[1][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s19/COUT
22.974 | 0.000 | tNET | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/CIN
23.022 | 0.048 | tINS | RR | 1 | R7C79[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s20/COUT
23.022 | 0.000 | tNET | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/CIN
23.070 | 0.048 | tINS | RR | 1 | R7C79[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s21/COUT
23.070 | 0.000 | tNET | RR | 1 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/CIN
23.118 | 0.048 | tINS | RF | 2 | R7C80[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n178_s22/COUT
23.364 | 0.246 | tNET | FF | 1 | R7C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s2/I2
23.864 | 0.500 | tINS | FR | 1 | R7C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/n247_s2/F
23.864 | 0.000 | tNET | RR | 1 | R7C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.485 | 0.361 | tNET | RR | 1 | R7C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0/CLK
20.450 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0
20.389 | -0.061 | tSu |  | 1 | R7C80[3][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_T_Auto_ADJ/dir_1_s0

Path Statistics:

Clock Skew | -0.380
Setup Relationship | 5.000
Logic Level | 5
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 1.571, 19.641%; route: 6.047, 75.589%; tC2Q: 0.382, 4.770%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.361, 100.000%

### Path11

Path Summary:

Slack | -2.587
Data Arrival Time | 22.981
Data Required Time | 20.394
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_2_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[2]
22.981 | 6.329 | tNET | RR | 1 | R5C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.490 | 0.365 | tNET | RR | 1 | R5C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_2_s0/CLK
20.455 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_2_s0
20.394 | -0.061 | tSu |  | 1 | R5C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_2_s0

Path Statistics:

Clock Skew | -0.375
Setup Relationship | 5.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 0.406, 5.705%; route: 6.329, 88.933%; tC2Q: 0.382, 5.362%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.365, 100.000%

### Path12

Path Summary:

Slack | -2.180
Data Arrival Time | 5.146
Data Required Time | 2.966
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/stop_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.055 | 0.373 | tNET | RR | 1 | R2C83[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/stop_reg_2_s0/CLK
1.422 | 0.367 | tC2Q | RR | 1 | R2C83[2][B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/stop_reg_2_s0/Q
5.146 | 3.724 | tNET | RR | 1 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CEN

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
2.500 | 2.500 |  |  |  |  | active clock edge time
2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
3.183 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
3.183 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
3.148 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen
2.966 | -0.182 | tSu |  | 1 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen

Path Statistics:

Clock Skew | -0.373
Setup Relationship | 2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.373, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.724, 91.024%; tC2Q: 0.367, 8.976%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000%

### Path13

Path Summary:

Slack | -1.948
Data Arrival Time | 12.194
Data Required Time | 10.246
From | rgb2gray/PROC_FORMULA.sum_10_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_324_G[2]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.020 | 0.338 | tNET | RR | 1 | R35C73[3][A] | rgb2gray/PROC_FORMULA.sum_10_s0/CLK
1.388 | 0.367 | tC2Q | RR | 3 | R35C73[3][A] | rgb2gray/PROC_FORMULA.sum_10_s0/Q
5.662 | 4.274 | tNET | RR | 1 | R7C35[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n163_s2/I1
6.027 | 0.365 | tINS | RF | 512 | R7C35[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n163_s2/F
12.194 | 6.167 | tNET | FF | 1 | R16C28[1][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_324_G[2]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.336 | 0.336 | tNET | RR | 1 | R16C28[1][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_324_G[2]_s0/CLK
10.301 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_324_G[2]_s0
10.246 | -0.055 | tSu |  | 1 | R16C28[1][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_324_G[2]_s0

Path Statistics:

Clock Skew | -0.684
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.338, 100.000%
Arrival Data Path Delay | cell: 0.365, 3.265%; route: 10.441, 93.449%; tC2Q: 0.367, 3.286%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.336, 100.000%

### Path14

Path Summary:

Slack | -1.897
Data Arrival Time | 11.922
Data Required Time | 10.025
From | rgb2gray/PROC_FORMULA.sum_11_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_429_G[3]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.020 | 0.338 | tNET | RR | 1 | R35C73[3][B] | rgb2gray/PROC_FORMULA.sum_11_s0/CLK
1.388 | 0.367 | tC2Q | RR | 5 | R35C73[3][B] | rgb2gray/PROC_FORMULA.sum_11_s0/Q
6.108 | 4.721 | tNET | RR | 1 | R8C31[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n162_s2/I1
6.473 | 0.365 | tINS | RF | 512 | R8C31[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n162_s2/F
11.922 | 5.449 | tNET | FF | 1 | R36C22[3][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_429_G[3]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.340 | 0.340 | tNET | RR | 1 | R36C22[3][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_429_G[3]_s0/CLK
10.305 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_429_G[3]_s0
10.025 | -0.280 | tSu |  | 1 | R36C22[3][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_429_G[3]_s0

Path Statistics:

Clock Skew | -0.681
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.338, 100.000%
Arrival Data Path Delay | cell: 0.365, 3.346%; route: 10.170, 93.286%; tC2Q: 0.367, 3.368%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.340, 100.000%

### Path15

Path Summary:

Slack | -1.895
Data Arrival Time | 22.291
Data Required Time | 20.396
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_7_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 9 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[7]
22.291 | 5.639 | tNET | RR | 1 | R4C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.492 | 0.368 | tNET | RR | 1 | R4C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_7_s0/CLK
20.457 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_7_s0
20.396 | -0.061 | tSu |  | 1 | R4C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_7_s0

Path Statistics:

Clock Skew | -0.372
Setup Relationship | 5.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 0.406, 6.318%; route: 5.639, 87.744%; tC2Q: 0.382, 5.938%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%

### Path16

Path Summary:

Slack | -1.886
Data Arrival Time | 12.132
Data Required Time | 10.246
From | rgb2gray/PROC_FORMULA.sum_14_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_311_G[6]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.019 | 0.336 | tNET | RR | 1 | R34C73[3][B] | rgb2gray/PROC_FORMULA.sum_14_s0/CLK
1.386 | 0.367 | tC2Q | RR | 5 | R34C73[3][B] | rgb2gray/PROC_FORMULA.sum_14_s0/Q
5.257 | 3.871 | tNET | RR | 1 | R7C33[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n159_s2/I1
5.624 | 0.367 | tINS | RF | 512 | R7C33[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n159_s2/F
12.132 | 6.508 | tNET | FF | 1 | R34C34[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_311_G[6]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.336 | 0.336 | tNET | RR | 1 | R34C34[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_311_G[6]_s0/CLK
10.301 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_311_G[6]_s0
10.246 | -0.055 | tSu |  | 1 | R34C34[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_311_G[6]_s0

Path Statistics:

Clock Skew | -0.683
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.336, 100.000%
Arrival Data Path Delay | cell: 0.367, 3.304%; route: 10.379, 93.392%; tC2Q: 0.367, 3.304%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.336, 100.000%

### Path17

Path Summary:

Slack | -1.865
Data Arrival Time | 12.143
Data Required Time | 10.278
From | rgb2gray/PROC_FORMULA.sum_14_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_302_G[6]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.019 | 0.336 | tNET | RR | 1 | R34C73[3][B] | rgb2gray/PROC_FORMULA.sum_14_s0/CLK
1.386 | 0.367 | tC2Q | RR | 5 | R34C73[3][B] | rgb2gray/PROC_FORMULA.sum_14_s0/Q
5.257 | 3.871 | tNET | RR | 1 | R7C33[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n159_s2/I1
5.624 | 0.367 | tINS | RF | 512 | R7C33[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n159_s2/F
12.143 | 6.518 | tNET | FF | 1 | R22C32[2][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_302_G[6]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.368 | 0.368 | tNET | RR | 1 | R22C32[2][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_302_G[6]_s0/CLK
10.333 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_302_G[6]_s0
10.278 | -0.055 | tSu |  | 1 | R22C32[2][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_302_G[6]_s0

Path Statistics:

Clock Skew | -0.651
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.336, 100.000%
Arrival Data Path Delay | cell: 0.367, 3.301%; route: 10.390, 93.398%; tC2Q: 0.367, 3.301%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%

### Path18

Path Summary:

Slack | -1.822
Data Arrival Time | 12.059
Data Required Time | 10.237
From | rgb2gray/PROC_FORMULA.sum_10_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_443_G[2]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.020 | 0.338 | tNET | RR | 1 | R35C73[3][A] | rgb2gray/PROC_FORMULA.sum_10_s0/CLK
1.388 | 0.367 | tC2Q | RR | 3 | R35C73[3][A] | rgb2gray/PROC_FORMULA.sum_10_s0/Q
5.662 | 4.274 | tNET | RR | 1 | R7C35[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n163_s2/I1
6.027 | 0.365 | tINS | RF | 512 | R7C35[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n163_s2/F
12.059 | 6.032 | tNET | FF | 1 | R16C23[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_443_G[2]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.327 | 0.327 | tNET | RR | 1 | R16C23[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_443_G[2]_s0/CLK
10.292 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_443_G[2]_s0
10.237 | -0.055 | tSu |  | 1 | R16C23[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_443_G[2]_s0

Path Statistics:

Clock Skew | -0.693
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.338, 100.000%
Arrival Data Path Delay | cell: 0.365, 3.305%; route: 10.307, 93.369%; tC2Q: 0.367, 3.326%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000%

### Path19

Path Summary:

Slack | -1.821
Data Arrival Time | 12.042
Data Required Time | 10.221
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_167_G[6]_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
0.868 | 0.367 | tC2Q | RR | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
3.324 | 2.455 | tNET | RR | 1 | R5C30[1][A] | g_rst_p_s2/I0
3.819 | 0.496 | tINS | RR | 16 | R5C30[1][A] | g_rst_p_s2/F
4.580 | 0.761 | tNET | RR | 1 | R8C32[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/n159_s2/I0
4.832 | 0.252 | tINS | RR | 512 | R8C32[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/n159_s2/F
12.042 | 7.210 | tNET | RR | 1 | R30C48[1][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_167_G[6]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.317 | 0.317 | tNET | RR | 1 | R30C48[1][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_167_G[6]_s0/CLK
10.282 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_167_G[6]_s0
10.221 | -0.061 | tSu |  | 1 | R30C48[1][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_167_G[6]_s0

Path Statistics:

Clock Skew | -0.184
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.748, 6.478%; route: 10.426, 90.340%; tC2Q: 0.367, 3.182%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.317, 100.000%

### Path20

Path Summary:

Slack | -1.821
Data Arrival Time | 12.042
Data Required Time | 10.221
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_71_G[6]_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
0.868 | 0.367 | tC2Q | RR | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
3.324 | 2.455 | tNET | RR | 1 | R5C30[1][A] | g_rst_p_s2/I0
3.819 | 0.496 | tINS | RR | 16 | R5C30[1][A] | g_rst_p_s2/F
4.580 | 0.761 | tNET | RR | 1 | R8C32[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/n159_s2/I0
4.832 | 0.252 | tINS | RR | 512 | R8C32[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/n159_s2/F
12.042 | 7.210 | tNET | RR | 1 | R30C48[0][A] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_71_G[6]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.317 | 0.317 | tNET | RR | 1 | R30C48[0][A] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_71_G[6]_s0/CLK
10.282 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_71_G[6]_s0
10.221 | -0.061 | tSu |  | 1 | R30C48[0][A] | sobel/shift_register_2taps/shift_reg_ram_inst2/u_RAM_based_shift_reg/mem_mem_RAMREG_71_G[6]_s0

Path Statistics:

Clock Skew | -0.184
Setup Relationship | 10.000
Logic Level | 3
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.748, 6.478%; route: 10.426, 90.340%; tC2Q: 0.367, 3.182%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.317, 100.000%

### Path21

Path Summary:

Slack | -1.817
Data Arrival Time | 22.211
Data Required Time | 20.394
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_6_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[6]
22.211 | 5.558 | tNET | RR | 1 | R5C86[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_6_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.490 | 0.365 | tNET | RR | 1 | R5C86[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_6_s0/CLK
20.455 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_6_s0
20.394 | -0.061 | tSu |  | 1 | R5C86[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_6_s0

Path Statistics:

Clock Skew | -0.375
Setup Relationship | 5.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 0.406, 6.398%; route: 5.558, 87.589%; tC2Q: 0.382, 6.013%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.365, 100.000%

### Path22

Path Summary:

Slack | -1.780
Data Arrival Time | 12.027
Data Required Time | 10.248
From | rgb2gray/PROC_FORMULA.sum_14_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_263_G[6]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.019 | 0.336 | tNET | RR | 1 | R34C73[3][B] | rgb2gray/PROC_FORMULA.sum_14_s0/CLK
1.386 | 0.367 | tC2Q | RR | 5 | R34C73[3][B] | rgb2gray/PROC_FORMULA.sum_14_s0/Q
5.257 | 3.871 | tNET | RR | 1 | R7C33[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n159_s2/I1
5.624 | 0.367 | tINS | RF | 512 | R7C33[3][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n159_s2/F
12.027 | 6.403 | tNET | FF | 1 | R35C34[1][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_263_G[6]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.338 | 0.338 | tNET | RR | 1 | R35C34[1][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_263_G[6]_s0/CLK
10.303 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_263_G[6]_s0
10.248 | -0.055 | tSu |  | 1 | R35C34[1][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_263_G[6]_s0

Path Statistics:

Clock Skew | -0.681
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.336, 100.000%
Arrival Data Path Delay | cell: 0.367, 3.336%; route: 10.274, 93.329%; tC2Q: 0.367, 3.336%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.338, 100.000%

### Path23

Path Summary:

Slack | -1.770
Data Arrival Time | 12.016
Data Required Time | 10.246
From | rgb2gray/PROC_FORMULA.sum_10_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_281_G[2]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.020 | 0.338 | tNET | RR | 1 | R35C73[3][A] | rgb2gray/PROC_FORMULA.sum_10_s0/CLK
1.388 | 0.367 | tC2Q | RR | 3 | R35C73[3][A] | rgb2gray/PROC_FORMULA.sum_10_s0/Q
5.662 | 4.274 | tNET | RR | 1 | R7C35[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n163_s2/I1
6.027 | 0.365 | tINS | RF | 512 | R7C35[2][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n163_s2/F
12.016 | 5.989 | tNET | FF | 1 | R16C26[2][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_281_G[2]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.336 | 0.336 | tNET | RR | 1 | R16C26[2][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_281_G[2]_s0/CLK
10.301 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_281_G[2]_s0
10.246 | -0.055 | tSu |  | 1 | R16C26[2][A] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_281_G[2]_s0

Path Statistics:

Clock Skew | -0.684
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.338, 100.000%
Arrival Data Path Delay | cell: 0.365, 3.318%; route: 10.264, 93.343%; tC2Q: 0.367, 3.340%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.336, 100.000%

### Path24

Path Summary:

Slack | -1.721
Data Arrival Time | 11.970
Data Required Time | 10.249
From | rgb2gray/PROC_FORMULA.sum_11_s0
To | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_471_G[3]_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | sobel/shift_register_2taps/clk_ce:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
1.020 | 0.338 | tNET | RR | 1 | R35C73[3][B] | rgb2gray/PROC_FORMULA.sum_11_s0/CLK
1.388 | 0.367 | tC2Q | RR | 5 | R35C73[3][B] | rgb2gray/PROC_FORMULA.sum_11_s0/Q
6.108 | 4.721 | tNET | RR | 1 | R8C31[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n162_s2/I1
6.473 | 0.365 | tINS | RF | 512 | R8C31[0][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/n162_s2/F
11.970 | 5.497 | tNET | FF | 1 | R36C20[1][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_471_G[3]_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
10.000 | 10.000 |  |  |  |  | active clock edge time
10.000 | 0.000 |  |  |  |  | sobel/shift_register_2taps/clk_ce
10.000 | 0.000 | tCL | RR | 8226 | TOPRIGHT | sobel/shift_register_2taps/DCE/CLKOUT
10.340 | 0.340 | tNET | RR | 1 | R36C20[1][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_471_G[3]_s0/CLK
10.305 | -0.035 | tUnc |  |  |  | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_471_G[3]_s0
10.249 | -0.055 | tSu |  | 1 | R36C20[1][B] | sobel/shift_register_2taps/shift_reg_ram_inst1/u_RAM_based_shift_reg/mem_mem_RAMREG_471_G[3]_s0

Path Statistics:

Clock Skew | -0.681
Setup Relationship | 10.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.338, 100.000%
Arrival Data Path Delay | cell: 0.365, 3.332%; route: 10.218, 93.315%; tC2Q: 0.367, 3.353%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.340, 100.000%

### Path25

Path Summary:

Slack | -1.720
Data Arrival Time | 22.116
Data Required Time | 20.396
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_5_s0
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
15.000 | 15.000 |  |  |  |  | active clock edge time
15.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
15.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
15.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
15.865 | 0.182 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
16.246 | 0.382 | tNET | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/CLKIN
16.652 | 0.406 | tINS | RR | 8 | DDRDLLM_TL | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_dll/STEP[5]
22.116 | 5.464 | tNET | RR | 1 | R4C86[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
20.000 | 20.000 |  |  |  |  | active clock edge time
20.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.492 | 0.368 | tNET | RR | 1 | R4C86[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_5_s0/CLK
20.457 | -0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_5_s0
20.396 | -0.061 | tSu |  | 1 | R4C86[0][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/dll_step_base_5_s0

Path Statistics:

Clock Skew | -0.372
Setup Relationship | 5.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.182, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay | cell: 0.406, 6.495%; route: 5.464, 87.401%; tC2Q: 0.382, 6.104%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.368, 100.000%

### Hold Analysis Report

#### Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -0.311
Data Arrival Time | 0.705
Data Required Time | 1.016
From | u_dvi_encoder/encr/dout_6_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.166 | 0.166 | tNET | RR | 1 | R34C81[3][A] | u_dvi_encoder/encr/dout_6_s0/CLK
0.339 | 0.173 | tC2Q | RR | 1 | R34C81[3][A] | u_dvi_encoder/encr/dout_6_s0/Q
0.458 | 0.119 | tNET | RR | 1 | R34C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/n80_s0/I0
0.705 | 0.247 | tINS | RF | 1 | R34C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/n80_s0/F
0.705 | 0.000 | tNET | FF | 1 | R34C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.980 | 0.166 | tNET | RR | 1 | R34C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/CLK
1.015 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0
1.016 | 0.001 | tHld |  | 1 | R34C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.247, 45.880%; route: 0.119, 22.049%; tC2Q: 0.173, 32.071%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%

### Path2

Path Summary:

Slack | -0.266
Data Arrival Time | 0.566
Data Required Time | 0.832
From | u_dvi_encoder/encb/dout_9_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.160 | 0.160 | tNET | RR | 1 | R32C87[1][B] | u_dvi_encoder/encb/dout_9_s0/CLK
0.332 | 0.173 | tC2Q | RR | 1 | R32C87[1][B] | u_dvi_encoder/encb/dout_9_s0/Q
0.566 | 0.234 | tNET | RR | 1 | R32C84[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.978 | 0.164 | tNET | RR | 1 | R32C84[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0/CLK
1.013 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0
0.832 | -0.181 | tHld |  | 1 | R32C84[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0

Path Statistics:

Clock Skew | 0.819
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.160, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.234, 57.522%; tC2Q: 0.173, 42.478%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%

### Path3

Path Summary:

Slack | -0.256
Data Arrival Time | 0.573
Data Required Time | 0.829
From | u_dvi_encoder/encr/dout_8_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.172 | 0.172 | tNET | RR | 1 | R35C80[2][A] | u_dvi_encoder/encr/dout_8_s0/CLK
0.345 | 0.173 | tC2Q | RR | 1 | R35C80[2][A] | u_dvi_encoder/encr/dout_8_s0/Q
0.573 | 0.228 | tNET | RR | 1 | R34C82[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.975 | 0.161 | tNET | RR | 1 | R34C82[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0/CLK
1.010 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0
0.829 | -0.181 | tHld |  | 1 | R34C82[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0

Path Statistics:

Clock Skew | 0.803
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.172, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.161, 100.000%

### Path4

Path Summary:

Slack | -0.253
Data Arrival Time | 0.764
Data Required Time | 1.016
From | u_dvi_encoder/encr/dout_3_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.166 | 0.166 | tNET | RR | 1 | R34C81[3][B] | u_dvi_encoder/encr/dout_3_s0/CLK
0.339 | 0.173 | tC2Q | RR | 1 | R34C81[3][B] | u_dvi_encoder/encr/dout_3_s0/Q
0.458 | 0.119 | tNET | RR | 1 | R34C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/I0
0.764 | 0.306 | tINS | RF | 1 | R34C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/F
0.764 | 0.000 | tNET | FF | 1 | R34C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.980 | 0.166 | tNET | RR | 1 | R34C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/CLK
1.015 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0
1.016 | 0.001 | tHld |  | 1 | R34C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.306, 51.205%; route: 0.119, 19.880%; tC2Q: 0.173, 28.916%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%

### Path5

Path Summary:

Slack | -0.252
Data Arrival Time | 0.702
Data Required Time | 0.954
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.318 | 0.193 | tNET | RR | 1 | R3C84[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/CLK
0.491 | 0.173 | tC2Q | RR | 8 | R3C84[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q
0.702 | 0.211 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/CALIB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem
0.954 | 0.000 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew | 0.601
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.193, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.211, 55.000%; tC2Q: 0.173, 45.000%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path6

Path Summary:

Slack | -0.243
Data Arrival Time | 0.588
Data Required Time | 0.830
From | u_dvi_encoder/encg/dout_8_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.169 | 0.169 | tNET | RR | 1 | R36C81[1][A] | u_dvi_encoder/encg/dout_8_s0/CLK
0.342 | 0.173 | tC2Q | RR | 1 | R36C81[1][A] | u_dvi_encoder/encg/dout_8_s0/Q
0.588 | 0.246 | tNET | RR | 1 | R35C82[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.977 | 0.163 | tNET | RR | 1 | R35C82[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0/CLK
1.012 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0
0.830 | -0.181 | tHld |  | 1 | R35C82[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0

Path Statistics:

Clock Skew | 0.808
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.246, 58.739%; tC2Q: 0.173, 41.261%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.163, 100.000%

### Path7

Path Summary:

Slack | -0.201
Data Arrival Time | 0.814
Data Required Time | 1.015
From | u_dvi_encoder/encr/dout_4_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.160 | 0.160 | tNET | RR | 1 | R33C82[2][A] | u_dvi_encoder/encr/dout_4_s0/CLK
0.332 | 0.173 | tC2Q | RR | 1 | R33C82[2][A] | u_dvi_encoder/encr/dout_4_s0/Q
0.566 | 0.234 | tNET | RR | 1 | R33C79[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/n81_s0/I0
0.814 | 0.247 | tINS | RF | 1 | R33C79[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/n81_s0/F
0.814 | 0.000 | tNET | FF | 1 | R33C79[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.978 | 0.164 | tNET | RR | 1 | R33C79[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/CLK
1.013 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0
1.015 | 0.001 | tHld |  | 1 | R33C79[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0

Path Statistics:

Clock Skew | 0.819
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.160, 100.000%
Arrival Data Path Delay | cell: 0.247, 37.798%; route: 0.234, 35.780%; tC2Q: 0.173, 26.422%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%

### Path8

Path Summary:

Slack | -0.148
Data Arrival Time | 0.683
Data Required Time | 0.830
From | u_dvi_encoder/encr/dout_9_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.164 | 0.164 | tNET | RR | 1 | R33C83[3][B] | u_dvi_encoder/encr/dout_9_s0/CLK
0.337 | 0.173 | tC2Q | RR | 2 | R33C83[3][B] | u_dvi_encoder/encr/dout_9_s0/Q
0.683 | 0.346 | tNET | RR | 1 | R35C82[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.977 | 0.163 | tNET | RR | 1 | R35C82[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0/CLK
1.012 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0
0.830 | -0.181 | tHld |  | 1 | R35C82[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0

Path Statistics:

Clock Skew | 0.812
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.346, 66.667%; tC2Q: 0.173, 33.333%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.163, 100.000%

### Path9

Path Summary:

Slack | -0.147
Data Arrival Time | 0.689
Data Required Time | 0.835
From | u_dvi_encoder/encg/dout_9_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.174 | 0.174 | tNET | RR | 1 | R36C84[3][B] | u_dvi_encoder/encg/dout_9_s0/CLK
0.347 | 0.173 | tC2Q | RR | 1 | R36C84[3][B] | u_dvi_encoder/encg/dout_9_s0/Q
0.689 | 0.342 | tNET | RR | 1 | R35C83[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.981 | 0.167 | tNET | RR | 1 | R35C83[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0/CLK
1.016 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0
0.835 | -0.181 | tHld |  | 1 | R35C83[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0

Path Statistics:

Clock Skew | 0.808
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.174, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.342, 66.434%; tC2Q: 0.173, 33.566%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.167, 100.000%

### Path10

Path Summary:

Slack | -0.142
Data Arrival Time | 0.872
Data Required Time | 1.015
From | u_dvi_encoder/encr/dout_7_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.160 | 0.160 | tNET | RR | 1 | R33C82[3][A] | u_dvi_encoder/encr/dout_7_s0/CLK
0.332 | 0.173 | tC2Q | RR | 1 | R33C82[3][A] | u_dvi_encoder/encr/dout_7_s0/Q
0.566 | 0.234 | tNET | RR | 1 | R33C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/I0
0.872 | 0.306 | tINS | RF | 1 | R33C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/F
0.872 | 0.000 | tNET | FF | 1 | R33C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.978 | 0.164 | tNET | RR | 1 | R33C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/CLK
1.013 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0
1.015 | 0.001 | tHld |  | 1 | R33C79[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0

Path Statistics:

Clock Skew | 0.819
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.160, 100.000%
Arrival Data Path Delay | cell: 0.306, 42.929%; route: 0.234, 32.828%; tC2Q: 0.173, 24.242%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%

### Path11

Path Summary:

Slack | -0.128
Data Arrival Time | 0.888
Data Required Time | 1.016
From | u_dvi_encoder/encg/dout_6_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.171 | 0.171 | tNET | RR | 1 | R34C84[2][A] | u_dvi_encoder/encg/dout_6_s0/CLK
0.344 | 0.173 | tC2Q | RR | 1 | R34C84[2][A] | u_dvi_encoder/encg/dout_6_s0/Q
0.705 | 0.361 | tNET | RR | 1 | R34C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/n70_s0/I0
0.888 | 0.184 | tINS | RF | 1 | R34C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/n70_s0/F
0.888 | 0.000 | tNET | FF | 1 | R34C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.980 | 0.166 | tNET | RR | 1 | R34C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/CLK
1.015 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0
1.016 | 0.001 | tHld |  | 1 | R34C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0

Path Statistics:

Clock Skew | 0.809
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.171, 100.000%
Arrival Data Path Delay | cell: 0.184, 25.585%; route: 0.361, 50.334%; tC2Q: 0.173, 24.080%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%

### Path12

Path Summary:

Slack | -0.125
Data Arrival Time | 0.894
Data Required Time | 1.019
From | u_dvi_encoder/encb/dout_5_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.169 | 0.169 | tNET | RR | 1 | R33C88[0][B] | u_dvi_encoder/encb/dout_5_s0/CLK
0.342 | 0.173 | tC2Q | RR | 1 | R33C88[0][B] | u_dvi_encoder/encb/dout_5_s0/Q
0.647 | 0.305 | tNET | RR | 1 | R33C80[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/n66_s0/I0
0.894 | 0.247 | tINS | RF | 1 | R33C80[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/n66_s0/F
0.894 | 0.000 | tNET | FF | 1 | R33C80[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.983 | 0.169 | tNET | RR | 1 | R33C80[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/CLK
1.018 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0
1.019 | 0.001 | tHld |  | 1 | R33C80[0][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%
Arrival Data Path Delay | cell: 0.247, 34.106%; route: 0.305, 42.053%; tC2Q: 0.173, 23.841%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%

### Path13

Path Summary:

Slack | -0.122
Data Arrival Time | 0.894
Data Required Time | 1.016
From | u_dvi_encoder/encg/dout_2_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.171 | 0.171 | tNET | RR | 1 | R34C84[0][A] | u_dvi_encoder/encg/dout_2_s0/CLK
0.344 | 0.173 | tC2Q | RR | 1 | R34C84[0][A] | u_dvi_encoder/encg/dout_2_s0/Q
0.711 | 0.367 | tNET | RR | 1 | R34C79[2][B] | u_dvi_encoder/serdes_4b_10to1_inst/n72_s0/I0
0.894 | 0.184 | tINS | RF | 1 | R34C79[2][B] | u_dvi_encoder/serdes_4b_10to1_inst/n72_s0/F
0.894 | 0.000 | tNET | FF | 1 | R34C79[2][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.980 | 0.166 | tNET | RR | 1 | R34C79[2][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0/CLK
1.015 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0
1.016 | 0.001 | tHld |  | 1 | R34C79[2][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0

Path Statistics:

Clock Skew | 0.809
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.171, 100.000%
Arrival Data Path Delay | cell: 0.184, 25.373%; route: 0.367, 50.746%; tC2Q: 0.173, 23.881%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%

### Path14

Path Summary:

Slack | -0.119
Data Arrival Time | 0.899
Data Required Time | 1.018
From | u_dvi_encoder/encr/dout_9_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.164 | 0.164 | tNET | RR | 1 | R33C83[3][B] | u_dvi_encoder/encr/dout_9_s0/CLK
0.337 | 0.173 | tC2Q | RR | 2 | R33C83[3][B] | u_dvi_encoder/encr/dout_9_s0/Q
0.652 | 0.314 | tNET | RR | 1 | R35C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/n82_s0/I0
0.899 | 0.247 | tINS | RF | 1 | R35C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/n82_s0/F
0.899 | 0.000 | tNET | FF | 1 | R35C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.981 | 0.167 | tNET | RR | 1 | R35C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/CLK
1.016 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0
1.018 | 0.001 | tHld |  | 1 | R35C79[1][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0

Path Statistics:

Clock Skew | 0.817
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%
Arrival Data Path Delay | cell: 0.247, 33.660%; route: 0.314, 42.810%; tC2Q: 0.173, 23.529%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.167, 100.000%

### Path15

Path Summary:

Slack | -0.117
Data Arrival Time | 0.837
Data Required Time | 0.954
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.318 | 0.193 | tNET | RR | 1 | R3C84[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/CLK
0.491 | 0.173 | tC2Q | RR | 8 | R3C84[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q
0.837 | 0.347 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/CALIB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem
0.954 | 0.000 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew | 0.601
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.193, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.347, 66.744%; tC2Q: 0.173, 33.256%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path16

Path Summary:

Slack | -0.080
Data Arrival Time | 0.935
Data Required Time | 1.015
From | u_dvi_encoder/encg/dout_1_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.160 | 0.160 | tNET | RR | 1 | R33C86[2][A] | u_dvi_encoder/encg/dout_1_s0/CLK
0.332 | 0.173 | tC2Q | RR | 1 | R33C86[2][A] | u_dvi_encoder/encg/dout_1_s0/Q
0.637 | 0.305 | tNET | RR | 1 | R33C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/n78_s0/I0
0.935 | 0.298 | tINS | RF | 1 | R33C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/n78_s0/F
0.935 | 0.000 | tNET | FF | 1 | R33C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.978 | 0.164 | tNET | RR | 1 | R33C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/CLK
1.013 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0
1.015 | 0.001 | tHld |  | 1 | R33C79[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0

Path Statistics:

Clock Skew | 0.819
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.160, 100.000%
Arrival Data Path Delay | cell: 0.298, 38.390%; route: 0.305, 39.319%; tC2Q: 0.173, 22.291%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%

### Path17

Path Summary:

Slack | -0.080
Data Arrival Time | 0.940
Data Required Time | 1.019
From | u_dvi_encoder/encb/dout_3_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.169 | 0.169 | tNET | RR | 1 | R33C88[1][B] | u_dvi_encoder/encb/dout_3_s0/CLK
0.342 | 0.173 | tC2Q | RR | 1 | R33C88[1][B] | u_dvi_encoder/encb/dout_3_s0/Q
0.756 | 0.414 | tNET | RR | 1 | R33C80[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/n67_s0/I0
0.940 | 0.184 | tINS | RF | 1 | R33C80[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/n67_s0/F
0.940 | 0.000 | tNET | FF | 1 | R33C80[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.983 | 0.169 | tNET | RR | 1 | R33C80[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/CLK
1.018 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0
1.019 | 0.001 | tHld |  | 1 | R33C80[0][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%
Arrival Data Path Delay | cell: 0.184, 23.832%; route: 0.414, 53.738%; tC2Q: 0.173, 22.430%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%

### Path18

Path Summary:

Slack | -0.080
Data Arrival Time | 0.940
Data Required Time | 1.019
From | u_dvi_encoder/encb/dout_6_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.169 | 0.169 | tNET | RR | 1 | R33C88[1][A] | u_dvi_encoder/encb/dout_6_s0/CLK
0.342 | 0.173 | tC2Q | RR | 1 | R33C88[1][A] | u_dvi_encoder/encb/dout_6_s0/Q
0.756 | 0.414 | tNET | RR | 1 | R33C80[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/n60_s0/I0
0.940 | 0.184 | tINS | RF | 1 | R33C80[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/n60_s0/F
0.940 | 0.000 | tNET | FF | 1 | R33C80[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.983 | 0.169 | tNET | RR | 1 | R33C80[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/CLK
1.018 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0
1.019 | 0.001 | tHld |  | 1 | R33C80[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%
Arrival Data Path Delay | cell: 0.184, 23.832%; route: 0.414, 53.738%; tC2Q: 0.173, 22.430%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%

### Path19

Path Summary:

Slack | -0.075
Data Arrival Time | 0.757
Data Required Time | 0.832
From | u_dvi_encoder/encb/dout_8_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.164 | 0.164 | tNET | RR | 1 | R33C89[2][A] | u_dvi_encoder/encb/dout_8_s0/CLK
0.337 | 0.173 | tC2Q | RR | 1 | R33C89[2][A] | u_dvi_encoder/encb/dout_8_s0/Q
0.757 | 0.420 | tNET | RR | 1 | R32C84[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.978 | 0.164 | tNET | RR | 1 | R32C84[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0/CLK
1.013 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0
0.832 | -0.181 | tHld |  | 1 | R32C84[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.420, 70.850%; tC2Q: 0.173, 29.150%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%

### Path20

Path Summary:

Slack | -0.058
Data Arrival Time | 0.958
Data Required Time | 1.016
From | u_dvi_encoder/encg/dout_3_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.171 | 0.171 | tNET | RR | 1 | R34C84[0][B] | u_dvi_encoder/encg/dout_3_s0/CLK
0.344 | 0.173 | tC2Q | RR | 1 | R34C84[0][B] | u_dvi_encoder/encg/dout_3_s0/Q
0.711 | 0.367 | tNET | RR | 1 | R34C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/n77_s0/I0
0.958 | 0.247 | tINS | RF | 1 | R34C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/n77_s0/F
0.958 | 0.000 | tNET | FF | 1 | R34C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.980 | 0.166 | tNET | RR | 1 | R34C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0/CLK
1.015 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0
1.016 | 0.001 | tHld |  | 1 | R34C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0

Path Statistics:

Clock Skew | 0.809
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.171, 100.000%
Arrival Data Path Delay | cell: 0.247, 31.402%; route: 0.367, 46.646%; tC2Q: 0.173, 21.951%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%

### Path21

Path Summary:

Slack | -0.052
Data Arrival Time | 0.962
Data Required Time | 1.015
From | u_dvi_encoder/encr/dout_5_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.160 | 0.160 | tNET | RR | 1 | R33C82[3][B] | u_dvi_encoder/encr/dout_5_s0/CLK
0.332 | 0.173 | tC2Q | RR | 1 | R33C82[3][B] | u_dvi_encoder/encr/dout_5_s0/Q
0.656 | 0.324 | tNET | RR | 1 | R33C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/I0
0.962 | 0.306 | tINS | RF | 1 | R33C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/F
0.962 | 0.000 | tNET | FF | 1 | R33C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.978 | 0.164 | tNET | RR | 1 | R33C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/CLK
1.013 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0
1.015 | 0.001 | tHld |  | 1 | R33C79[1][B] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0

Path Statistics:

Clock Skew | 0.819
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.160, 100.000%
Arrival Data Path Delay | cell: 0.306, 38.117%; route: 0.324, 40.359%; tC2Q: 0.173, 21.525%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.164, 100.000%

### Path22

Path Summary:

Slack | -0.045
Data Arrival Time | 0.909
Data Required Time | 0.954
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.320 | 0.195 | tNET | RR | 1 | R2C82[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/CLK
0.493 | 0.173 | tC2Q | RR | 8 | R2C82[2][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/ides_calib_d_s0/Q
0.909 | 0.416 | tNET | RR | 1 | IOT72[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/CALIB

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT72[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem
0.954 | 0.000 | tHld |  | 1 | IOT72[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew | 0.599
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.195, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.416, 70.672%; tC2Q: 0.173, 29.328%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path23

Path Summary:

Slack | -0.016
Data Arrival Time | 1.003
Data Required Time | 1.019
From | u_dvi_encoder/encb/dout_4_s0
To | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
0.000 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
0.169 | 0.169 | tNET | RR | 1 | R33C88[2][A] | u_dvi_encoder/encb/dout_4_s0/CLK
0.342 | 0.173 | tC2Q | RR | 1 | R33C88[2][A] | u_dvi_encoder/encb/dout_4_s0/Q
0.756 | 0.414 | tNET | RR | 1 | R33C80[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/n61_s0/I0
1.003 | 0.247 | tINS | RF | 1 | R33C80[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/n61_s0/F
1.003 | 0.000 | tNET | FF | 1 | R33C80[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | pll/PLLA_inst/CLKOUT0.default_gen_clk
0.814 | 0.814 | tCL | RR | 50 | PLL_L[0] | pll/PLLA_inst/CLKOUT0
0.983 | 0.169 | tNET | RR | 1 | R33C80[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/CLK
1.018 | 0.035 | tUnc |  |  |  | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0
1.019 | 0.001 | tHld |  | 1 | R33C80[2][A] | u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0

Path Statistics:

Clock Skew | 0.814
Hold Relationship | 0.000
Logic Level | 2
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%
Arrival Data Path Delay | cell: 0.247, 29.640%; route: 0.414, 49.640%; tC2Q: 0.173, 20.719%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.169, 100.000%

### Path24

Path Summary:

Slack | -0.015
Data Arrival Time | 0.699
Data Required Time | 0.714
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.299 | 0.174 | tNET | RR | 1 | R26C77[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/CLK
0.471 | 0.173 | tC2Q | RR | 1 | R26C77[0][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_3_s0/Q
0.699 | 0.228 | tNET | RR | 1 | R27C78[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.860 | 0.178 | tNET | RR | 1 | R27C78[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0/CLK
0.895 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0
0.714 | -0.181 | tHld |  | 1 | R27C78[2][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_3_s0

Path Statistics:

Clock Skew | 0.562
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.174, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.178, 100.000%

### Path25

Path Summary:

Slack | -0.015
Data Arrival Time | 0.699
Data Required Time | 0.714
From | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0
To | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.299 | 0.174 | tNET | RR | 1 | R26C77[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/CLK
0.471 | 0.173 | tC2Q | RR | 1 | R26C77[0][A] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.rptr_4_s0/Q
0.699 | 0.228 | tNET | RR | 1 | R27C78[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/D

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.860 | 0.178 | tNET | RR | 1 | R27C78[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0/CLK
0.895 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0
0.714 | -0.181 | tHld |  | 1 | R27C78[1][B] | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.wq1_rptr_4_s0

Path Statistics:

Clock Skew | 0.562
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.174, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.228, 56.886%; tC2Q: 0.173, 43.114%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.178, 100.000%

### Recovery Analysis Report

#### Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | -2.528
Data Arrival Time | 63.085
Data Required Time | 60.557
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_6_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C82[2][A] | disp_driver/hcount_r_6_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.926 | 0.320 | tNET | RR | 1 | R32C82[2][A] | disp_driver/hcount_r_6_s0/CLK
60.891 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_6_s0
60.557 | -0.334 | tSu |  | 1 | R32C82[2][A] | disp_driver/hcount_r_6_s0

Path Statistics:

Clock Skew | -0.182
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.320, 100.000%

### Path2

Path Summary:

Slack | -2.528
Data Arrival Time | 63.085
Data Required Time | 60.557
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_7_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C82[1][A] | disp_driver/hcount_r_7_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.926 | 0.320 | tNET | RR | 1 | R32C82[1][A] | disp_driver/hcount_r_7_s0/CLK
60.891 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_7_s0
60.557 | -0.334 | tSu |  | 1 | R32C82[1][A] | disp_driver/hcount_r_7_s0

Path Statistics:

Clock Skew | -0.182
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.320, 100.000%

### Path3

Path Summary:

Slack | -2.528
Data Arrival Time | 63.085
Data Required Time | 60.557
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_8_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C82[1][B] | disp_driver/hcount_r_8_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.926 | 0.320 | tNET | RR | 1 | R32C82[1][B] | disp_driver/hcount_r_8_s0/CLK
60.891 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_8_s0
60.557 | -0.334 | tSu |  | 1 | R32C82[1][B] | disp_driver/hcount_r_8_s0

Path Statistics:

Clock Skew | -0.182
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.320, 100.000%

### Path4

Path Summary:

Slack | -2.524
Data Arrival Time | 63.092
Data Required Time | 60.568
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encb/cnt_1_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.092 | 2.238 | tNET | FF | 1 | R36C90[2][B] | u_dvi_encoder/encb/cnt_1_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.937 | 0.331 | tNET | RR | 1 | R36C90[2][B] | u_dvi_encoder/encb/cnt_1_s0/CLK
60.902 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encb/cnt_1_s0
60.568 | -0.334 | tSu |  | 1 | R36C90[2][B] | u_dvi_encoder/encb/cnt_1_s0

Path Statistics:

Clock Skew | -0.171
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.238, 86.383%; tC2Q: 0.353, 13.617%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.331, 100.000%

### Path5

Path Summary:

Slack | -2.524
Data Arrival Time | 63.092
Data Required Time | 60.568
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encb/cnt_3_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.092 | 2.238 | tNET | FF | 1 | R36C90[3][A] | u_dvi_encoder/encb/cnt_3_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.937 | 0.331 | tNET | RR | 1 | R36C90[3][A] | u_dvi_encoder/encb/cnt_3_s0/CLK
60.902 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encb/cnt_3_s0
60.568 | -0.334 | tSu |  | 1 | R36C90[3][A] | u_dvi_encoder/encb/cnt_3_s0

Path Statistics:

Clock Skew | -0.171
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.238, 86.383%; tC2Q: 0.353, 13.617%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.331, 100.000%

### Path6

Path Summary:

Slack | -2.524
Data Arrival Time | 63.087
Data Required Time | 60.563
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encr/dout_4_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.087 | 2.233 | tNET | FF | 1 | R33C82[2][A] | u_dvi_encoder/encr/dout_4_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.931 | 0.325 | tNET | RR | 1 | R33C82[2][A] | u_dvi_encoder/encr/dout_4_s0/CLK
60.896 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encr/dout_4_s0
60.563 | -0.334 | tSu |  | 1 | R33C82[2][A] | u_dvi_encoder/encr/dout_4_s0

Path Statistics:

Clock Skew | -0.176
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.233, 86.354%; tC2Q: 0.353, 13.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.325, 100.000%

### Path7

Path Summary:

Slack | -2.524
Data Arrival Time | 63.087
Data Required Time | 60.563
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encr/dout_5_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.087 | 2.233 | tNET | FF | 1 | R33C82[3][B] | u_dvi_encoder/encr/dout_5_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.931 | 0.325 | tNET | RR | 1 | R33C82[3][B] | u_dvi_encoder/encr/dout_5_s0/CLK
60.896 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encr/dout_5_s0
60.563 | -0.334 | tSu |  | 1 | R33C82[3][B] | u_dvi_encoder/encr/dout_5_s0

Path Statistics:

Clock Skew | -0.176
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.233, 86.354%; tC2Q: 0.353, 13.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.325, 100.000%

### Path8

Path Summary:

Slack | -2.524
Data Arrival Time | 63.087
Data Required Time | 60.563
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encr/dout_7_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.087 | 2.233 | tNET | FF | 1 | R33C82[3][A] | u_dvi_encoder/encr/dout_7_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.931 | 0.325 | tNET | RR | 1 | R33C82[3][A] | u_dvi_encoder/encr/dout_7_s0/CLK
60.896 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encr/dout_7_s0
60.563 | -0.334 | tSu |  | 1 | R33C82[3][A] | u_dvi_encoder/encr/dout_7_s0

Path Statistics:

Clock Skew | -0.176
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.233, 86.354%; tC2Q: 0.353, 13.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.325, 100.000%

### Path9

Path Summary:

Slack | -2.524
Data Arrival Time | 63.089
Data Required Time | 60.564
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encg/cnt_3_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.089 | 2.234 | tNET | FF | 1 | R34C86[2][A] | u_dvi_encoder/encg/cnt_3_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.933 | 0.327 | tNET | RR | 1 | R34C86[2][A] | u_dvi_encoder/encg/cnt_3_s0/CLK
60.898 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encg/cnt_3_s0
60.564 | -0.334 | tSu |  | 1 | R34C86[2][A] | u_dvi_encoder/encg/cnt_3_s0

Path Statistics:

Clock Skew | -0.174
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.234, 86.364%; tC2Q: 0.353, 13.636%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.327, 100.000%

### Path10

Path Summary:

Slack | -2.524
Data Arrival Time | 63.087
Data Required Time | 60.563
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encg/cnt_4_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.087 | 2.233 | tNET | FF | 1 | R33C86[3][A] | u_dvi_encoder/encg/cnt_4_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.931 | 0.325 | tNET | RR | 1 | R33C86[3][A] | u_dvi_encoder/encg/cnt_4_s0/CLK
60.896 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encg/cnt_4_s0
60.563 | -0.334 | tSu |  | 1 | R33C86[3][A] | u_dvi_encoder/encg/cnt_4_s0

Path Statistics:

Clock Skew | -0.176
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.233, 86.354%; tC2Q: 0.353, 13.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.325, 100.000%

### Path11

Path Summary:

Slack | -2.524
Data Arrival Time | 63.087
Data Required Time | 60.563
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encg/dout_1_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.087 | 2.233 | tNET | FF | 1 | R33C86[2][A] | u_dvi_encoder/encg/dout_1_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.931 | 0.325 | tNET | RR | 1 | R33C86[2][A] | u_dvi_encoder/encg/dout_1_s0/CLK
60.896 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encg/dout_1_s0
60.563 | -0.334 | tSu |  | 1 | R33C86[2][A] | u_dvi_encoder/encg/dout_1_s0

Path Statistics:

Clock Skew | -0.176
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.233, 86.354%; tC2Q: 0.353, 13.646%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.325, 100.000%

### Path12

Path Summary:

Slack | -2.524
Data Arrival Time | 63.090
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encb/cnt_2_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.090 | 2.236 | tNET | FF | 1 | R35C90[2][B] | u_dvi_encoder/encb/cnt_2_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R35C90[2][B] | u_dvi_encoder/encb/cnt_2_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encb/cnt_2_s0
60.566 | -0.334 | tSu |  | 1 | R35C90[2][B] | u_dvi_encoder/encb/cnt_2_s0

Path Statistics:

Clock Skew | -0.172
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.236, 86.373%; tC2Q: 0.353, 13.627%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path13

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | u_dvi_encoder/encb/dout_9_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C87[1][B] | u_dvi_encoder/encb/dout_9_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C87[1][B] | u_dvi_encoder/encb/dout_9_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | u_dvi_encoder/encb/dout_9_s0
60.566 | -0.334 | tSu |  | 1 | R32C87[1][B] | u_dvi_encoder/encb/dout_9_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path14

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/vcount_r_0_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C83[0][A] | disp_driver/vcount_r_0_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C83[0][A] | disp_driver/vcount_r_0_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/vcount_r_0_s0
60.566 | -0.334 | tSu |  | 1 | R32C83[0][A] | disp_driver/vcount_r_0_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path15

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/vcount_r_1_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C83[0][B] | disp_driver/vcount_r_1_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C83[0][B] | disp_driver/vcount_r_1_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/vcount_r_1_s0
60.566 | -0.334 | tSu |  | 1 | R32C83[0][B] | disp_driver/vcount_r_1_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path16

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/vcount_r_2_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C83[1][B] | disp_driver/vcount_r_2_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C83[1][B] | disp_driver/vcount_r_2_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/vcount_r_2_s0
60.566 | -0.334 | tSu |  | 1 | R32C83[1][B] | disp_driver/vcount_r_2_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path17

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/vcount_r_3_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C83[1][A] | disp_driver/vcount_r_3_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C83[1][A] | disp_driver/vcount_r_3_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/vcount_r_3_s0
60.566 | -0.334 | tSu |  | 1 | R32C83[1][A] | disp_driver/vcount_r_3_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path18

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/vcount_r_4_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C83[2][A] | disp_driver/vcount_r_4_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C83[2][A] | disp_driver/vcount_r_4_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/vcount_r_4_s0
60.566 | -0.334 | tSu |  | 1 | R32C83[2][A] | disp_driver/vcount_r_4_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path19

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/vcount_r_8_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C83[2][B] | disp_driver/vcount_r_8_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C83[2][B] | disp_driver/vcount_r_8_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/vcount_r_8_s0
60.566 | -0.334 | tSu |  | 1 | R32C83[2][B] | disp_driver/vcount_r_8_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path20

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_0_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C85[0][B] | disp_driver/hcount_r_0_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C85[0][B] | disp_driver/hcount_r_0_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_0_s0
60.566 | -0.334 | tSu |  | 1 | R32C85[0][B] | disp_driver/hcount_r_0_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path21

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_1_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C85[2][A] | disp_driver/hcount_r_1_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C85[2][A] | disp_driver/hcount_r_1_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_1_s0
60.566 | -0.334 | tSu |  | 1 | R32C85[2][A] | disp_driver/hcount_r_1_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path22

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_2_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C85[2][B] | disp_driver/hcount_r_2_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C85[2][B] | disp_driver/hcount_r_2_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_2_s0
60.566 | -0.334 | tSu |  | 1 | R32C85[2][B] | disp_driver/hcount_r_2_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path23

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_3_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C85[1][A] | disp_driver/hcount_r_3_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C85[1][A] | disp_driver/hcount_r_3_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_3_s0
60.566 | -0.334 | tSu |  | 1 | R32C85[1][A] | disp_driver/hcount_r_3_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path24

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_4_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C85[1][B] | disp_driver/hcount_r_4_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C85[1][B] | disp_driver/hcount_r_4_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_4_s0
60.566 | -0.334 | tSu |  | 1 | R32C85[1][B] | disp_driver/hcount_r_4_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Path25

Path Summary:

Slack | -2.519
Data Arrival Time | 63.085
Data Required Time | 60.566
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0
To | disp_driver/hcount_r_5_s0
Launch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.000 | 60.000 |  |  |  |  | active clock edge time
60.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
60.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
60.501 | 0.377 | tNET | RR | 1 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/CLK
60.854 | 0.353 | tC2Q | RF | 585 | R4C87[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_init/ddr_init_complete_d_3_s0/Q
63.085 | 2.231 | tNET | FF | 1 | R32C85[0][A] | disp_driver/hcount_r_5_s0/CLEAR

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
60.606 | 60.606 |  |  |  |  | active clock edge time
60.606 | 0.000 |  |  |  |  | u_clkdiv/CLKOUT.default_gen_clk
60.606 | 0.000 | tCL | RR | 190 | RIGHTSIDE[0] | u_clkdiv/CLKOUT
60.935 | 0.329 | tNET | RR | 1 | R32C85[0][A] | disp_driver/hcount_r_5_s0/CLK
60.900 | -0.035 | tUnc |  |  |  | disp_driver/hcount_r_5_s0
60.566 | -0.334 | tSu |  | 1 | R32C85[0][A] | disp_driver/hcount_r_5_s0

Path Statistics:

Clock Skew | -0.173
Setup Relationship | 0.606
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.377, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.231, 86.345%; tC2Q: 0.353, 13.655%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.329, 100.000%

### Removal Analysis Report

#### Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

### Path1

Path Summary:

Slack | 0.589
Data Arrival Time | 2.063
Data Required Time | 1.475
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.287 | 0.368 | tINS | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.287 | 0.000 | tNET | RR | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.322 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.475 | 0.153 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.439
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.524, 86.698%; route: 0.080, 13.302%

### Path2

Path Summary:

Slack | 0.589
Data Arrival Time | 2.063
Data Required Time | 1.475
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C60 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.287 | 0.368 | tINS | RR | 1 | R0C60 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
1.287 | 0.000 | tNET | RR | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
1.322 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.475 | 0.153 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.439
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.524, 86.698%; route: 0.080, 13.302%

### Path3

Path Summary:

Slack | 0.678
Data Arrival Time | 2.063
Data Required Time | 1.386
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.198 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.198 | 0.000 | tNET | RR | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
1.233 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.386 | 0.153 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | 0.350
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.435, 84.400%; route: 0.080, 15.600%

### Path4

Path Summary:

Slack | 0.678
Data Arrival Time | 2.063
Data Required Time | 1.386
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.198 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.198 | 0.000 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
1.233 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.386 | 0.153 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | 0.350
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.435, 84.400%; route: 0.080, 15.600%

### Path5

Path Summary:

Slack | 0.678
Data Arrival Time | 2.063
Data Required Time | 1.386
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.198 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.198 | 0.000 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
1.233 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.386 | 0.153 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | 0.350
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.435, 84.400%; route: 0.080, 15.600%

### Path6

Path Summary:

Slack | 0.678
Data Arrival Time | 2.063
Data Required Time | 1.386
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.198 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.198 | 0.000 | tNET | RR | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
1.233 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.386 | 0.153 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | 0.350
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.435, 84.400%; route: 0.080, 15.600%

### Path7

Path Summary:

Slack | 0.678
Data Arrival Time | 2.063
Data Required Time | 1.386
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT76[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
1.198 | 0.279 | tINS | RR | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
1.198 | 0.000 | tNET | RR | 1 | IOT76[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem/TCLK
1.233 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem
1.386 | 0.153 | tHld |  | 1 | IOT76[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[4].u_oser8_mem

Path Statistics:

Clock Skew | 0.350
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.435, 84.400%; route: 0.080, 15.600%

### Path8

Path Summary:

Slack | 0.957
Data Arrival Time | 2.063
Data Required Time | 1.107
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.107 | 0.153 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.071
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path9

Path Summary:

Slack | 0.957
Data Arrival Time | 2.063
Data Required Time | 1.107
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
1.107 | 0.153 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.071
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path10

Path Summary:

Slack | 0.957
Data Arrival Time | 2.063
Data Required Time | 1.107
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
1.107 | 0.153 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | 0.071
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path11

Path Summary:

Slack | 0.957
Data Arrival Time | 2.063
Data Required Time | 1.107
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
1.107 | 0.153 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | 0.071
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path12

Path Summary:

Slack | 0.957
Data Arrival Time | 2.063
Data Required Time | 1.107
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
1.107 | 0.153 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | 0.071
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path13

Path Summary:

Slack | 0.957
Data Arrival Time | 2.063
Data Required Time | 1.107
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
0.683 | 0.683 | tCL | RR | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
0.683 | 0.000 | tNET | RR | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
0.839 | 0.156 | tINS | RR | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
0.919 | 0.080 | tNET | RR | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/FCLK
0.954 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
1.107 | 0.153 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | 0.071
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.156, 65.990%; route: 0.080, 34.010%

### Path14

Path Summary:

Slack | 1.671
Data Arrival Time | 2.064
Data Required Time | 0.393
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.205 | 0.080 | tNET | RR | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/PCLK
0.240 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
0.393 | 0.153 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | -0.643
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.080, 100.000%

### Path15

Path Summary:

Slack | 1.675
Data Arrival Time | 2.063
Data Required Time | 0.388
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.200 | 0.076 | tNET | RR | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.235 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.388 | 0.153 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | -0.648
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.076, 100.000%

### Path16

Path Summary:

Slack | 1.675
Data Arrival Time | 2.063
Data Required Time | 0.388
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.200 | 0.076 | tNET | RR | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/PCLK
0.235 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
0.388 | 0.153 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | -0.648
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.076, 100.000%

### Path17

Path Summary:

Slack | 1.675
Data Arrival Time | 2.063
Data Required Time | 0.388
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.200 | 0.076 | tNET | RR | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/PCLK
0.235 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
0.388 | 0.153 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | -0.648
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.076, 100.000%

### Path18

Path Summary:

Slack | 1.680
Data Arrival Time | 2.064
Data Required Time | 0.383
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.195 | 0.071 | tNET | RR | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/PCLK
0.230 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
0.383 | 0.153 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | -0.653
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.071, 100.000%

### Path19

Path Summary:

Slack | 1.680
Data Arrival Time | 2.064
Data Required Time | 0.383
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
0.125 | 0.125 | tCL | RR | 3225 | TOPSIDE[0] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
0.195 | 0.071 | tNET | RR | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/PCLK
0.230 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
0.383 | 0.153 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | -0.653
Hold Relationship | 0.000
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.071, 100.000%

### Path20

Path Summary:

Slack | 3.064
Data Arrival Time | 2.063
Data Required Time | -1.000
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
-1.817 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
-1.817 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.655 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.575 | 0.080 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.186 | 0.389 | tINS | FF | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-1.186 | 0.000 | tNET | FF | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-1.151 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-1.000 | 0.151 | tHld |  | 1 | IOT80[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.466
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.551, 87.266%; route: 0.080, 12.734%

### Path21

Path Summary:

Slack | 3.064
Data Arrival Time | 2.063
Data Required Time | -1.000
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
-1.817 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
-1.817 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.655 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.575 | 0.080 | tNET | FF | 1 | R0C60 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.186 | 0.389 | tINS | FF | 1 | R0C60 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW270
-1.186 | 0.000 | tNET | FF | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen/TCLK
-1.151 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen
-1.000 | 0.151 | tHld |  | 1 | IOT61[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs_gen

Path Statistics:

Clock Skew | 0.466
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.551, 87.266%; route: 0.080, 12.734%

### Path22

Path Summary:

Slack | 3.164
Data Arrival Time | 2.063
Data Required Time | -1.100
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
-1.817 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
-1.817 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.655 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.575 | 0.080 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.286 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.286 | 0.000 | tNET | FF | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem/TCLK
-1.251 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem
-1.100 | 0.151 | tHld |  | 1 | IOT85[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[8].u_oser8_mem

Path Statistics:

Clock Skew | 0.366
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.451, 84.870%; route: 0.080, 15.130%

### Path23

Path Summary:

Slack | 3.164
Data Arrival Time | 2.063
Data Required Time | -1.100
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
-1.817 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
-1.817 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.655 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.575 | 0.080 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.286 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.286 | 0.000 | tNET | FF | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem/TCLK
-1.251 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem
-1.100 | 0.151 | tHld |  | 1 | IOT83[B] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[7].u_oser8_mem

Path Statistics:

Clock Skew | 0.366
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.451, 84.870%; route: 0.080, 15.130%

### Path24

Path Summary:

Slack | 3.164
Data Arrival Time | 2.063
Data Required Time | -1.100
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
-1.817 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
-1.817 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.655 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.575 | 0.080 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.286 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.286 | 0.000 | tNET | FF | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem/TCLK
-1.251 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem
-1.100 | 0.151 | tHld |  | 1 | IOT83[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[6].u_oser8_mem

Path Statistics:

Clock Skew | 0.366
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.451, 84.870%; route: 0.080, 15.130%

### Path25

Path Summary:

Slack | 3.164
Data Arrival Time | 2.063
Data Required Time | -1.100
From | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0
To | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
Launch Clk | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk:[R]
Latch Clk | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk:[F]

Data Arrival Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
0.000 | 0.000 |  |  |  |  | active clock edge time
0.000 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
0.683 | 0.683 | tCL | RR | 516 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT0
0.848 | 0.166 | tNET | RR | 1 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/CLK
1.021 | 0.173 | tC2Q | RR | 2196 | R29C86[1][A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/ddr_rsti_reg_2_s0/Q
2.063 | 1.043 | tNET | RR | 2 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/RESET

Data Required Path:

AT | DELAY | TYPE | RF | FANOUT | LOC | NODE
--- | --- | --- | --- | --- | --- | ---
-2.500 | -2.500 |  |  |  |  | active clock edge time
-2.500 | 0.000 |  |  |  |  | ddr3_pll/PLLA_inst/CLKOUT1.default_gen_clk
-1.817 | 0.683 | tCL | FF | 1 | PLL_B | ddr3_pll/PLLA_inst/CLKOUT1
-1.817 | 0.000 | tNET | FF | 3 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKIN
-1.655 | 0.162 | tINS | FF | 64 | - | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclk_dhcen/CLKOUT
-1.575 | 0.080 | tNET | FF | 1 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK
-1.286 | 0.289 | tINS | FF | 9 | R0C82 | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/DQSW0
-1.286 | 0.000 | tNET | FF | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem/TCLK
-1.251 | 0.035 | tUnc |  |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem
-1.100 | 0.151 | tHld |  | 1 | IOT76[A] | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/oserdes_gen[5].u_oser8_mem

Path Statistics:

Clock Skew | 0.366
Hold Relationship | -2.500
Logic Level | 1
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.166, 100.000%
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.043, 85.781%; tC2Q: 0.173, 14.219%
Required Clock Path Delay | cell: 0.451, 84.870%; route: 0.080, 15.130%

## Minimum Pulse Width Report:

#### Report Command:report_min_pulse_width -nworst 10 -detail

### MPW1

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects: | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
10.683 | 0.683 | tCL | FF | ddr3_pll/PLLA_inst/CLKOUT0
11.028 | 0.345 | tNET | FF | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
20.683 | 0.683 | tCL | RR | ddr3_pll/PLLA_inst/CLKOUT0
20.854 | 0.172 | tNET | RR | image_stitche_x/correct_set_pro.image1_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB

### MPW2

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects: | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
10.683 | 0.683 | tCL | FF | ddr3_pll/PLLA_inst/CLKOUT0
11.028 | 0.345 | tNET | FF | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
20.683 | 0.683 | tCL | RR | ddr3_pll/PLLA_inst/CLKOUT0
20.854 | 0.172 | tNET | RR | image_stitche_x/correct_set_pro.image2_buffer/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA

### MPW3

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
Objects: | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
10.683 | 0.683 | tCL | FF | ddr3_pll/PLLA_inst/CLKOUT0
11.028 | 0.345 | tNET | FF | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_pll/PLLA_inst/CLKOUT0.default_gen_clk
20.683 | 0.683 | tCL | RR | ddr3_pll/PLLA_inst/CLKOUT0
20.854 | 0.172 | tNET | RR | ddr3_ctrl_2port/fifo_ddr3_adapter/wr_data_fifo/fifo_inst/Big.mem_Big.mem_0_0_s/CLKA

### MPW4

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_2_s/CLKA

### MPW5

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_1_s/CLKA

### MPW6

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

### MPW7

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_2_s/CLKB

### MPW8

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_out_fifo/mem4_mem4_0_3_s/CLKB

### MPW9

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKB

### MPW10

MPW Summary:

Slack: | 8.826
Actual Width: | 9.826
Required Width: | 1.000
Type: | Low Pulse Width
Clock: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
Objects: | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s

Late clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
10.000 | 0.000 |  |  | active clock edge time
10.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
10.125 | 0.125 | tCL | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
10.470 | 0.345 | tNET | FF | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA

Early clock Path:

AT | DELAY | TYPE | RF | NODE
--- | --- | --- | --- | ---
20.000 | 0.000 |  |  | active clock edge time
20.000 | 0.000 |  |  | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk
20.125 | 0.125 | tCL | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT
20.296 | 0.172 | tNET | RR | ddr3_ctrl_2port/your_instance_name/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/mem_mem_0_3_s/CLKA

## High Fanout Nets Report:

#### Report Command:report_high_fanout_nets -max_nets 10

FANOUT | NET NAME | WORST SLACK | MAX DELAY
--- | --- | --- | ---
8226 | clk_ce | -0.689 | 0.391
3225 | ui_clk | -2.528 | 0.382
2196 | ui_clk_sync_rst | -0.229 | 2.105
2072 | wbin[8] | -0.562 | 7.025
2072 | wbin[8] | -0.689 | 6.706
1049 | wbin[7] | -0.665 | 5.116
1049 | wbin[7] | -0.580 | 5.177
585 | led_d_6[1] | -1.821 | 2.824
547 | wbin[2] | 2.270 | 4.259
547 | wbin[2] | 0.104 | 4.963

## Route Congestions Report:

#### Report Command:report_route_congestion -max_grids 10

GRID LOC | ROUTE CONGESTIONS
--- | ---
R11C76 | 86.11%
R9C77 | 83.33%
R8C79 | 81.94%
R10C79 | 81.94%
R9C78 | 80.56%
R10C78 | 77.78%
R8C75 | 77.78%
R16C12 | 77.78%
R14C48 | 77.78%
R11C77 | 76.39%

## Timing Exceptions Report:

### Setup Analysis Report

#### Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Hold Analysis Report

#### Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Recovery Analysis Report

#### Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

### Removal Analysis Report

#### Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

#### No timing exceptions to report!

## Timing Constraints Report:

SDC Command Type | State | Detail Command
--- | --- | ---